uartt.tan.rpt

串口程序

+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C12Q240C8       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                                           ;
+------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; Clock Node Name                          ; Clock Setting Name ; Type       ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset    ; Phase offset ;
+------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; appl:inst1|altpll:altpll_component|_clk0 ;                    ; PLL output ; 24.0 MHz         ; 0.000 ns      ; 0.000 ns     ; clk      ; 12                    ; 25                  ; -2.054 ns ;              ;
; clk                                      ;                    ; User Pin   ; 50.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
+------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'appl:inst1|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                                                         ;
+-----------------------------------------+-----------------------------------------------------+----------------------------+--------------------------+------------------------------------------+------------------------------------------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                       ; To                       ; From Clock                               ; To Clock                                 ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+----------------------------+--------------------------+------------------------------------------+------------------------------------------+-----------------------------+---------------------------+-------------------------+
; 34.165 ns                               ; 133.32 MHz ( period = 7.501 ns )                    ; UART:inst|key_entry2       ; UART:inst|key_entry1     ; appl:inst1|altpll:altpll_component|_clk0 ; appl:inst1|altpll:altpll_component|_clk0 ; 41.666 ns                   ; 36.856 ns                 ; 2.691 ns                ;
; 35.403 ns                               ; 159.67 MHz ( period = 6.263 ns )                    ; UART:inst|cnt_delay[5]     ; UART:inst|cnt_delay[0]   ; appl:inst1|altpll:altpll_component|_clk0 ; appl:inst1|altpll:altpll_component|_clk0 ; 41.666 ns                   ; 41.405 ns                 ; 6.002 ns                ;
; 35.403 ns                               ; 159.67 MHz ( period = 6.263 ns )                    ; UART:inst|cnt_delay[5]     ; UART:inst|cnt_delay[18]  ; appl:inst1|altpll:altpll_component|_clk0 ; appl:inst1|altpll:altpll_component|_clk0 ; 41.666 ns                   ; 41.405 ns                 ; 6.002 ns                ;
; 35.838 ns                               ; 171.59 MHz ( period = 5.828 ns )                    ; UART:inst|key_entry2       ; UART:inst|txd_reg        ; appl:inst1|altpll:altpll_component|_clk0 ; appl:inst1|altpll:altpll_component|_clk0 ; 41.666 ns                   ; 41.405 ns                 ; 5.567 ns                ;
; 35.865 ns                               ; 172.38 MHz ( period = 5.801 ns )                    ; UART:inst|cnt_delay[5]     ; UART:inst|cnt_delay[8]   ; appl:inst1|altpll:altpll_component|_clk0 ; appl:inst1|altpll:altpll_component|_clk0 ; 41.666 ns                   ; 41.405 ns                 ; 5.540 ns                ;
; 35.876 ns                               ; 172.71 MHz ( period = 5.790 ns )                    ; UART:inst|cnt_delay[5]     ; UART:inst|cnt_delay[13]  ; appl:inst1|altpll:altpll_component|_clk0 ; appl:inst1|altpll:altpll_component|_clk0 ; 41.666 ns                   ; 41.405 ns                 ; 5.529 ns                ;
; 35.947 ns                               ; 174.86 MHz ( period = 5.719 ns )                    ; UART:inst|state_tras[2]    ; UART:inst|send_state[2]  ; appl:inst1|altpll:altpll_component|_clk0 ; appl:inst1|altpll:altpll_component|_clk0 ; 41.666 ns                   ; 41.405 ns                 ; 5.458 ns                ;
; 35.949 ns                               ; 174.92 MHz ( period = 5.717 ns )                    ; UART:inst|cnt_delay[15]    ; UART:inst|cnt_delay[0]   ; appl:inst1|altpll:altpll_component|_clk0 ; appl:inst1|altpll:altpll_component|_clk0 ; 41.666 ns                   ; 41.405 ns                 ; 5.456 ns                ;
; 35.949 ns                               ; 174.92 MHz ( period = 5.717 ns )                    ; UART:inst|cnt_delay[15]    ; UART:inst|cnt_delay[18]  ; appl:inst1|altpll:altpll_component|_clk0 ; appl:inst1|altpll:altpll_component|_clk0 ; 41.666 ns                   ; 41.405 ns                 ; 5.456 ns                ;
; 35.980 ns                               ; 175.87 MHz ( period = 5.686 ns )                    ; UART:inst|cnt_delay[6]     ; UART:inst|cnt_delay[0]   ; appl:inst1|altpll:altpll_component|_clk0 ; appl:inst1|altpll:altpll_component|_clk0 ; 41.666 ns                   ; 41.405 ns                 ; 5.425 ns                ;
; 35.980 ns                               ; 175.87 MHz ( period = 5.686 ns )                    ; UART:inst|cnt_delay[6]     ; UART:inst|cnt_delay[18]  ; appl:inst1|altpll:altpll_component|_clk0 ; appl:inst1|altpll:altpll_component|_clk0 ; 41.666 ns                   ; 41.405 ns                 ; 5.425 ns                ;