fenpin.vhd

FSK信号发生器

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fenpin is
 port(clk:in std_logic;
      clk0:buffer std_logic;
      clk1:buffer std_logic;
      clk2:buffer std_logic
      );
 end fenpin;
architecture rtl of fenpin is
signal cout0,cout1,cout2:integer range 0 to 9999;
begin
 process(clk)
   begin
    if clk'event and clk='1' then
      if cout0=9999 then
         clk0<=not clk0;
         cout0<=0;
      else cout0<=cout0+1;
      end if; 
     if cout1<=99 then
         clk1<=not clk1;
         cout1<=0;
      else cout1<=cout1+1;
      end if;
     if cout2<=49 then
         clk2<=not clk2;
        cout2<=0;
       else cout2<=cout2+1;
     end if;
    end if;
 end process;
end rtl;