📄 vgainterface.map.rpt
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; Logic elements by mode ; ;
; -- normal mode ; 77 ;
; -- arithmetic mode ; 21 ;
; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 0 ;
; -- asynchronous clear/load mode ; 49 ;
; ; ;
; Total registers ; 51 ;
; Total logic cells in carry chains ; 24 ;
; I/O pins ; 8 ;
; Total memory bits ; 16384 ;
; Maximum fan-out node ; reset ;
; Maximum fan-out ; 49 ;
; Total fan-out ; 407 ;
; Average fan-out ; 3.70 ;
+---------------------------------------------+-------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+-------------------------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------------------------------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; M4Ks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+-------------------------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------------------------------------------------+
; |vgainterface ; 98 (90) ; 51 ; 16384 ; 0 ; 8 ; 0 ; 47 (41) ; 27 (25) ; 24 (24) ; 24 (24) ; 0 (0) ; |vgainterface ;
; |tsinghua:u1| ; 8 (0) ; 2 ; 16384 ; 0 ; 0 ; 0 ; 6 (0) ; 2 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |vgainterface|tsinghua:u1 ;
; |altsyncram:altsyncram_component| ; 8 (0) ; 2 ; 16384 ; 0 ; 0 ; 0 ; 6 (0) ; 2 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |vgainterface|tsinghua:u1|altsyncram:altsyncram_component ;
; |altsyncram_6h41:auto_generated| ; 8 (2) ; 2 ; 16384 ; 0 ; 0 ; 0 ; 6 (0) ; 2 (2) ; 0 (0) ; 0 (0) ; 0 (0) ; |vgainterface|tsinghua:u1|altsyncram:altsyncram_component|altsyncram_6h41:auto_generated ;
; |decode_iga:deep_decode| ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (4) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |vgainterface|tsinghua:u1|altsyncram:altsyncram_component|altsyncram_6h41:auto_generated|decode_iga:deep_decode ;
; |mux_rab:mux2| ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |vgainterface|tsinghua:u1|altsyncram:altsyncram_component|altsyncram_6h41:auto_generated|mux_rab:mux2 ;
+-------------------------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ;
+---------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+-------+------------------+
; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
+---------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+-------+------------------+
; tsinghua:u1|altsyncram:altsyncram_component|altsyncram_6h41:auto_generated|ALTSYNCRAM ; AUTO ; ROM ; 16384 ; 1 ; -- ; -- ; 16384 ; vgainterface.mif ;
+---------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+-------+------------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 51 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 49 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 26 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+---------------------------------------------------------------------------------------------------+
; Source assignments for tsinghua:u1|altsyncram:altsyncram_component|altsyncram_6h41:auto_generated ;
+---------------------------------+--------------------+------+-------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+-------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+-------------------------------------+
+------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: tsinghua:u1|altsyncram:altsyncram_component ;
+------------------------------------+------------------+----------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------------------+------------------+----------------------------------+
; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; OPERATION_MODE ; ROM ; Untyped ;
; WIDTH_A ; 1 ; Integer ;
; WIDTHAD_A ; 14 ; Integer ;
; NUMWORDS_A ; 16384 ; Integer ;
; OUTDATA_REG_A ; UNREGISTERED ; Untyped ;
; ADDRESS_ACLR_A ; NONE ; Untyped ;
; OUTDATA_ACLR_A ; NONE ; Untyped ;
; WRCONTROL_ACLR_A ; NONE ; Untyped ;
; INDATA_ACLR_A ; NONE ; Untyped ;
; BYTEENA_ACLR_A ; NONE ; Untyped ;
; WIDTH_B ; 1 ; Untyped ;
; WIDTHAD_B ; 1 ; Untyped ;
; NUMWORDS_B ; 1 ; Untyped ;
; INDATA_REG_B ; CLOCK1 ; Untyped ;
; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
; ADDRESS_REG_B ; CLOCK1 ; Untyped ;
; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
; INDATA_ACLR_B ; NONE ; Untyped ;
; WRCONTROL_ACLR_B ; NONE ; Untyped ;
; ADDRESS_ACLR_B ; NONE ; Untyped ;
; OUTDATA_ACLR_B ; NONE ; Untyped ;
; RDCONTROL_ACLR_B ; NONE ; Untyped ;
; BYTEENA_ACLR_B ; NONE ; Untyped ;
; WIDTH_BYTEENA_A ; 1 ; Integer ;
; WIDTH_BYTEENA_B ; 1 ; Untyped ;
; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
; BYTE_SIZE ; 8 ; Untyped ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;
; INIT_FILE ; vgainterface.mif ; Untyped ;
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
; MAXIMUM_DEPTH ; 0 ; Untyped ;
; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
; DEVICE_FAMILY ; Cyclone ; Untyped ;
; CBXI_PARAMETER ; altsyncram_6h41 ; Untyped ;
+------------------------------------+------------------+----------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Fri Jun 01 00:34:55 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off vgainterface -c vgainterface
Info: Found 2 design units, including 1 entities, in source file vgainterface.vhd
Info: Found design unit 1: vgainterface-vgainterface
Info: Found entity 1: vgainterface
Info: Elaborating entity "vgainterface" for the top level hierarchy
Warning: Using design file tsinghua.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: tsinghua-SYN
Info: Found entity 1: tsinghua
Info: Elaborating entity "tsinghua" for hierarchy "tsinghua:u1"
Info: Found 1 design units, including 1 entities, in source file ../../../../libraries/megafunctions/altsyncram.tdf
Info: Found entity 1: altsyncram
Info: Elaborating entity "altsyncram" for hierarchy "tsinghua:u1|altsyncram:altsyncram_component"
Info: Elaborated megafunction instantiation "tsinghua:u1|altsyncram:altsyncram_component"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_6h41.tdf
Info: Found entity 1: altsyncram_6h41
Info: Elaborating entity "altsyncram_6h41" for hierarchy "tsinghua:u1|altsyncram:altsyncram_component|altsyncram_6h41:auto_generated"
Info: Found 1 design units, including 1 entities, in source file db/decode_iga.tdf
Info: Found entity 1: decode_iga
Info: Elaborating entity "decode_iga" for hierarchy "tsinghua:u1|altsyncram:altsyncram_component|altsyncram_6h41:auto_generated|decode_iga:deep_decode"
Info: Found 1 design units, including 1 entities, in source file db/mux_rab.tdf
Info: Found entity 1: mux_rab
Info: Elaborating entity "mux_rab" for hierarchy "tsinghua:u1|altsyncram:altsyncram_component|altsyncram_6h41:auto_generated|mux_rab:mux2"
Info: Implemented 110 device resources after synthesis - the final resource count might be different
Info: Implemented 3 input pins
Info: Implemented 5 output pins
Info: Implemented 98 logic cells
Info: Implemented 4 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
Info: Processing ended: Fri Jun 01 00:35:06 2007
Info: Elapsed time: 00:00:12
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