vgainterface.map.qmsg

用VHDL语言写的VGA 控制程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Jun 01 00:34:55 2007 " "Info: Processing started: Fri Jun 01 00:34:55 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off vgainterface -c vgainterface " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off vgainterface -c vgainterface" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "vgainterface.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file vgainterface.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 vgainterface-vgainterface " "Info: Found design unit 1: vgainterface-vgainterface" {  } { { "vgainterface.vhd" "" { Text "D:/altera/quartus60/program/VGA_example/VGA_test1/vgainterface/vgainterface.vhd" 20 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 vgainterface " "Info: Found entity 1: vgainterface" {  } { { "vgainterface.vhd" "" { Text "D:/altera/quartus60/program/VGA_example/VGA_test1/vgainterface/vgainterface.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "vgainterface " "Info: Elaborating entity \"vgainterface\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "tsinghua.vhd 2 1 " "Warning: Using design file tsinghua.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 tsinghua-SYN " "Info: Found design unit 1: tsinghua-SYN" {  } { { "tsinghua.vhd" "" { Text "D:/altera/quartus60/program/VGA_example/VGA_test1/vgainterface/tsinghua.vhd" 55 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 tsinghua " "Info: Found entity 1: tsinghua" {  } { { "tsinghua.vhd" "" { Text "D:/altera/quartus60/program/VGA_example/VGA_test1/vgainterface/tsinghua.vhd" 45 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tsinghua tsinghua:u1 " "Info: Elaborating entity \"tsinghua\" for hierarchy \"tsinghua:u1\"" {  } { { "vgainterface.vhd" "u1" { Text "D:/altera/quartus60/program/VGA_example/VGA_test1/vgainterface/vgainterface.vhd" 46 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../../libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 426 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram tsinghua:u1\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"tsinghua:u1\|altsyncram:altsyncram_component\"" {  } { { "tsinghua.vhd" "altsyncram_component" { Text "D:/altera/quartus60/program/VGA_example/VGA_test1/vgainterface/tsinghua.vhd" 86 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "tsinghua:u1\|altsyncram:altsyncram_component " "Info: Elaborated megafunction instantiation \"tsinghua:u1\|altsyncram:altsyncram_component\"" {  } { { "tsinghua.vhd" "" { Text "D:/altera/quartus60/program/VGA_example/VGA_test1/vgainterface/tsinghua.vhd" 86 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_6h41.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_6h41.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_6h41 " "Info: Found entity 1: altsyncram_6h41" {  } { { "db/altsyncram_6h41.tdf" "" { Text "D:/altera/quartus60/program/VGA_example/VGA_test1/vgainterface/db/altsyncram_6h41.tdf" 40 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_6h41 tsinghua:u1\|altsyncram:altsyncram_component\|altsyncram_6h41:auto_generated " "Info: Elaborating entity \"altsyncram_6h41\" for hierarchy \"tsinghua:u1\|altsyncram:altsyncram_component\|altsyncram_6h41:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 905 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_iga.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/decode_iga.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_iga " "Info: Found entity 1: decode_iga" {  } { { "db/decode_iga.tdf" "" { Text "D:/altera/quartus60/program/VGA_example/VGA_test1/vgainterface/db/decode_iga.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_iga tsinghua:u1\|altsyncram:altsyncram_component\|altsyncram_6h41:auto_generated\|decode_iga:deep_decode " "Info: Elaborating entity \"decode_iga\" for hierarchy \"tsinghua:u1\|altsyncram:altsyncram_component\|altsyncram_6h41:auto_generated\|decode_iga:deep_decode\"" {  } { { "db/altsyncram_6h41.tdf" "deep_decode" { Text "D:/altera/quartus60/program/VGA_example/VGA_test1/vgainterface/db/altsyncram_6h41.tdf" 48 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_rab.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mux_rab.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_rab " "Info: Found entity 1: mux_rab" {  } { { "db/mux_rab.tdf" "" { Text "D:/altera/quartus60/program/VGA_example/VGA_test1/vgainterface/db/mux_rab.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_rab tsinghua:u1\|altsyncram:altsyncram_component\|altsyncram_6h41:auto_generated\|mux_rab:mux2 " "Info: Elaborating entity \"mux_rab\" for hierarchy \"tsinghua:u1\|altsyncram:altsyncram_component\|altsyncram_6h41:auto_generated\|mux_rab:mux2\"" {  } { { "db/altsyncram_6h41.tdf" "mux2" { Text "D:/altera/quartus60/program/VGA_example/VGA_test1/vgainterface/db/altsyncram_6h41.tdf" 49 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "110 " "Info: Implemented 110 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "5 " "Info: Implemented 5 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "98 " "Info: Implemented 98 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0} { "Info" "ISCL_SCL_TM_RAMS" "4 " "Info: Implemented 4 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Jun 01 00:35:06 2007 " "Info: Processing ended: Fri Jun 01 00:35:06 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Info: Elapsed time: 00:00:12" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}