decode_iga.tdf

用VHDL语言写的VGA 控制程序

--lpm_decode CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone" LPM_DECODES=4 LPM_WIDTH=2 data enable eq
--VERSION_BEGIN 6.0 cbx_cycloneii 2006:02:07:15:19:20:SJ cbx_lpm_add_sub 2006:01:09:11:17:20:SJ cbx_lpm_compare 2006:01:09:11:15:40:SJ cbx_lpm_decode 2006:01:09:11:16:44:SJ cbx_mgl 2006:04:14:11:14:36:SJ cbx_stratix 2006:02:07:15:17:04:SJ cbx_stratixii 2006:03:03:09:35:36:SJ  VERSION_END


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--synthesis_resources = lut 4 
SUBDESIGN decode_iga
( 
	data[1..0]	:	input;
	enable	:	input;
	eq[3..0]	:	output;
) 
VARIABLE 
	data_wire[1..0]	: WIRE;
	enable_wire	: WIRE;
	eq_node[3..0]	: WIRE;
	eq_wire[3..0]	: WIRE;
	w_anode29w[2..0]	: WIRE;
	w_anode42w[2..0]	: WIRE;
	w_anode50w[2..0]	: WIRE;
	w_anode58w[2..0]	: WIRE;

BEGIN 
	data_wire[] = data[];
	enable_wire = enable;
	eq[] = eq_node[];
	eq_node[3..0] = eq_wire[3..0];
	eq_wire[] = ( w_anode58w[2..2], w_anode50w[2..2], w_anode42w[2..2], w_anode29w[2..2]);
	w_anode29w[] = ( (w_anode29w[1..1] & (! data_wire[1..1])), (w_anode29w[0..0] & (! data_wire[0..0])), enable_wire);
	w_anode42w[] = ( (w_anode42w[1..1] & (! data_wire[1..1])), (w_anode42w[0..0] & data_wire[0..0]), enable_wire);
	w_anode50w[] = ( (w_anode50w[1..1] & data_wire[1..1]), (w_anode50w[0..0] & (! data_wire[0..0])), enable_wire);
	w_anode58w[] = ( (w_anode58w[1..1] & data_wire[1..1]), (w_anode58w[0..0] & data_wire[0..0]), enable_wire);
END;
--VALID FILE