mux_gcb.tdf

用VHDL语言写的VGA 控制程序

--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone" LPM_SIZE=16 LPM_WIDTH=1 LPM_WIDTHS=4 data result sel
--VERSION_BEGIN 4.1 cbx_lpm_mux 2004:03:10:10:50:34:SJ cbx_mgl 2004:06:17:17:30:06:SJ  VERSION_END


--  Copyright (C) 1988-2002 Altera Corporation
--  Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
--  support information,  device programming or simulation file,  and any other
--  associated  documentation or information  provided by  Altera  or a partner
--  under  Altera's   Megafunction   Partnership   Program  may  be  used  only
--  to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
--  other  use  of such  megafunction  design,  netlist,  support  information,
--  device programming or simulation file,  or any other  related documentation
--  or information  is prohibited  for  any  other purpose,  including, but not
--  limited to  modification,  reverse engineering,  de-compiling, or use  with
--  any other  silicon devices,  unless such use is  explicitly  licensed under
--  a separate agreement with  Altera  or a megafunction partner.  Title to the
--  intellectual property,  including patents,  copyrights,  trademarks,  trade
--  secrets,  or maskworks,  embodied in any such megafunction design, netlist,
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--  related documentation or information provided by  Altera  or a megafunction
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--  party's intellectual property, are provided herein.



--synthesis_resources = lut 10 
SUBDESIGN mux_gcb
( 
	data[15..0]	:	input;
	result[0..0]	:	output;
	sel[3..0]	:	input;
) 
VARIABLE 
	result_node[0..0]	: WIRE;
	sel_ffs_wire[3..0]	: WIRE;
	sel_node[3..0]	: WIRE;
	w_data131w[3..0]	: WIRE;
	w_data132w[3..0]	: WIRE;
	w_data133w[3..0]	: WIRE;
	w_data134w[3..0]	: WIRE;
	w_data76w[15..0]	: WIRE;
	w_result126w	: WIRE;
	w_result127w	: WIRE;
	w_result128w	: WIRE;
	w_result129w	: WIRE;
	w_result130w	: WIRE;
	w_result140w	: WIRE;
	w_result141w	: WIRE;
	w_result161w	: WIRE;
	w_result162w	: WIRE;
	w_result178w	: WIRE;
	w_result179w	: WIRE;
	w_result195w	: WIRE;
	w_result196w	: WIRE;
	w_result212w	: WIRE;
	w_result77w	: WIRE;
	w_sel135w[1..0]	: WIRE;

BEGIN 
	result[] = result_node[];
	result_node[] = ( w_result77w);
	sel_ffs_wire[] = ( sel[3..0]);
	sel_node[] = ( sel_ffs_wire[3..2], sel[1..0]);
	w_data131w[3..0] = w_data76w[3..0];
	w_data132w[3..0] = w_data76w[7..4];
	w_data133w[3..0] = w_data76w[11..8];
	w_data134w[3..0] = w_data76w[15..12];
	w_data76w[] = ( data[15..0]);
	w_result126w = (((w_result128w & sel_node[2..2]) & (! w_result212w)) # (w_result212w & (w_result130w # (! sel_node[2..2]))));
	w_result127w = w_result140w;
	w_result128w = w_result161w;
	w_result129w = w_result178w;
	w_result130w = w_result195w;
	w_result140w = (((w_data131w[1..1] & w_sel135w[0..0]) & (! w_result141w)) # (w_result141w & (w_data131w[3..3] # (! w_sel135w[0..0]))));
	w_result141w = (((w_data131w[0..0] & (! w_sel135w[1..1])) & (! w_sel135w[0..0])) # (w_sel135w[1..1] & (w_sel135w[0..0] # w_data131w[2..2])));
	w_result161w = (((w_data132w[1..1] & w_sel135w[0..0]) & (! w_result162w)) # (w_result162w & (w_data132w[3..3] # (! w_sel135w[0..0]))));
	w_result162w = (((w_data132w[0..0] & (! w_sel135w[1..1])) & (! w_sel135w[0..0])) # (w_sel135w[1..1] & (w_sel135w[0..0] # w_data132w[2..2])));
	w_result178w = (((w_data133w[1..1] & w_sel135w[0..0]) & (! w_result179w)) # (w_result179w & (w_data133w[3..3] # (! w_sel135w[0..0]))));
	w_result179w = (((w_data133w[0..0] & (! w_sel135w[1..1])) & (! w_sel135w[0..0])) # (w_sel135w[1..1] & (w_sel135w[0..0] # w_data133w[2..2])));
	w_result195w = (((w_data134w[1..1] & w_sel135w[0..0]) & (! w_result196w)) # (w_result196w & (w_data134w[3..3] # (! w_sel135w[0..0]))));
	w_result196w = (((w_data134w[0..0] & (! w_sel135w[1..1])) & (! w_sel135w[0..0])) # (w_sel135w[1..1] & (w_sel135w[0..0] # w_data134w[2..2])));
	w_result212w = (((w_result127w & (! sel_node[3..3])) & (! sel_node[2..2])) # (sel_node[3..3] & (sel_node[2..2] # w_result129w)));
	w_result77w = w_result126w;
	w_sel135w[1..0] = sel_node[1..0];
END;
--VALID FILE