vgainterface.tan.rpt

用VHDL语言写的VGA 控制程序

; Number of source nodes to report per destination node ; 10                 ;      ;    ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;
; Number of paths to report                             ; 200                ;      ;    ;
; Run Minimum Analysis                                  ; On                 ;      ;    ;
; Use Minimum Timing Models                             ; Off                ;      ;    ;
; Report IO Paths Separately                            ; Off                ;      ;    ;
; Clock Analysis Only                                   ; Off                ;      ;    ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;
; Cut off read during write signal paths                ; On                 ;      ;    ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;
+-------------------------------------------------------+--------------------+------+----+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                    ;
+------------------------------+------------------------------------------+---------------+----------------------------------+--------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+------------+----------+--------------+
; Type                         ; Slack                                    ; Required Time ; Actual Time                      ; From                                                                                       ; To                                                                                                        ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+------------------------------------------+---------------+----------------------------------+--------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+------------+----------+--------------+
; Worst-case tco               ; N/A                                      ; None          ; 15.717 ns                        ; vga_vs_control~reg0                                                                        ; vga_vs_control                                                                                            ; clock0     ;          ; 0            ;
; Worst-case Minimum tco       ; N/A                                      ; None          ; 15.461 ns                        ; vga_read_dispaly~reg0                                                                      ; vga_read_dispaly                                                                                          ; clock0     ;          ; 0            ;
; Clock Setup: 'clock0'        ; N/A                                      ; None          ; 173.49 MHz ( period = 5.764 ns ) ; address[3]                                                                                 ; tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|ram_block1a1~porta_address_reg3 ; clock0     ; clock0   ; 0            ;
; Clock Setup: 'clock2'        ; N/A                                      ; None          ; 338.41 MHz ( period = 2.955 ns ) ; count_z[0]                                                                                 ; count_z[4]                                                                                                ; clock2     ; clock2   ; 0            ;
; Clock Hold: 'clock0'         ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|address_reg_a[0] ; vga_read                                                                                                  ; clock0     ; clock0   ; 6            ;
; Total number of failed paths ;                                          ;               ;                                  ;                                                                                            ;                                                                                                           ;            ;          ; 6            ;
+------------------------------+------------------------------------------+---------------+----------------------------------+--------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+------------+----------+--------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                               ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; clock0          ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
; clock2          ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clock0'                                                                                                                                                                                                                                                                                                                ;
+-----------------------------------------+-----------------------------------------------------+-------------+------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From        ; To                                                                                                         ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-------------+------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 173.49 MHz ( period = 5.764 ns )                    ; address[3]  ; tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|ram_block1a1~porta_address_reg3  ; clock0     ; clock0   ; None                        ; None                      ; None                    ;
; N/A                                     ; 173.76 MHz ( period = 5.755 ns )                    ; address[6]  ; tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|ram_block1a1~porta_address_reg6  ; clock0     ; clock0   ; None                        ; None                      ; None                    ;
; N/A                                     ; 174.25 MHz ( period = 5.739 ns )                    ; address[0]  ; tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|ram_block1a0~porta_address_reg0  ; clock0     ; clock0   ; None                        ; None                      ; None                    ;
; N/A                                     ; 174.34 MHz ( period = 5.736 ns )                    ; address[0]  ; tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|ram_block1a1~porta_address_reg0  ; clock0     ; clock0   ; None                        ; None                      ; None                    ;
; N/A                                     ; 174.43 MHz ( period = 5.733 ns )                    ; address[3]  ; tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|ram_block1a0~porta_address_reg3  ; clock0     ; clock0   ; None                        ; None                      ; None                    ;
; N/A                                     ; 174.70 MHz ( period = 5.724 ns )                    ; address[6]  ; tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|ram_block1a2~porta_address_reg6  ; clock0     ; clock0   ; None                        ; None                      ; None                    ;
; N/A                                     ; 174.76 MHz ( period = 5.722 ns )                    ; address[6]  ; tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|ram_block1a3~porta_address_reg6  ; clock0     ; clock0   ; None                        ; None                      ; None                    ;