vgainterface.fit.eqn

用VHDL语言写的VGA 控制程序

--A1L161Q is vga_hs_control~reg0 at LC_X11_Y12_N9
--operation mode is normal

A1L161Q_sload_eqn = vga_h_sync;
A1L161Q = DFFEA(A1L161Q_sload_eqn, GLOBAL(clock_25mhz), GLOBAL(reset), , , , );


--A1L861Q is vga_vs_control~reg0 at LC_X11_Y12_N2
--operation mode is normal

A1L861Q_lut_out = vga_v_sync;
A1L861Q = DFFEA(A1L861Q_lut_out, GLOBAL(clock_25mhz), GLOBAL(reset), , , , );


--A1L461Q is vga_read_dispaly~reg0 at LC_X11_Y12_N7
--operation mode is normal

A1L461Q_lut_out = vga_h_sync & vga_read & vga_v_sync;
A1L461Q = DFFEA(A1L461Q_lut_out, GLOBAL(clock_25mhz), GLOBAL(reset), , , , );


--A1L751Q is vga_green_dispaly~reg0 at LC_X11_Y12_N8
--operation mode is normal

A1L751Q_lut_out = vga_h_sync & vga_green & vga_v_sync;
A1L751Q = DFFEA(A1L751Q_lut_out, GLOBAL(clock_25mhz), GLOBAL(reset), , , , );


--A1L151Q is vga_blue_dispaly~reg0 at LC_X11_Y12_N6
--operation mode is normal

A1L151Q_lut_out = vga_h_sync & vga_blue & vga_v_sync;
A1L151Q = DFFEA(A1L151Q_lut_out, GLOBAL(clock_25mhz), GLOBAL(reset), , , , );


--vga_h_sync is vga_h_sync at LC_X11_Y12_N4
--operation mode is normal

vga_h_sync_lut_out = !count_x[8] & !count_x[7] # !count_x[9];
vga_h_sync = DFFEA(vga_h_sync_lut_out, GLOBAL(clock_25mhz), GLOBAL(reset), , , , );


--clock_25mhz is clock_25mhz at LC_X11_Y9_N2
--operation mode is normal

clock_25mhz_lut_out = !clock_25mhz;
clock_25mhz = DFFEA(clock_25mhz_lut_out, GLOBAL(clock0), GLOBAL(reset), , , , );


--vga_v_sync is vga_v_sync at LC_X11_Y12_N5
--operation mode is normal

vga_v_sync_lut_out = !A1L441;
vga_v_sync = DFFEA(vga_v_sync_lut_out, GLOBAL(clock_25mhz), GLOBAL(reset), , , , );


--vga_read is vga_read at LC_X12_Y10_N4
--operation mode is normal

vga_read_lut_out = !A1L531 & A1L561 & (count_z[4] # !A1L731);
vga_read = DFFEA(vga_read_lut_out, GLOBAL(clock_25mhz), GLOBAL(reset), , A1L141, , );


--vga_green is vga_green at LC_X12_Y10_N0
--operation mode is normal

vga_green_lut_out = A1L561 & (count_z[4] # !A1L851);
vga_green = DFFEA(vga_green_lut_out, GLOBAL(clock_25mhz), GLOBAL(reset), , A1L141, , );


--vga_blue is vga_blue at LC_X12_Y10_N9
--operation mode is normal

vga_blue_lut_out = E1L2 & (A1L351 # A1L451 & !A1L531);
vga_blue = DFFEA(vga_blue_lut_out, GLOBAL(clock_25mhz), GLOBAL(reset), , A1L141, , );


--count_x[8] is count_x[8] at LC_X15_Y11_N9
--operation mode is normal

count_x[8]_lut_out = !A1L741 & A1L84;
count_x[8] = DFFEA(count_x[8]_lut_out, GLOBAL(clock_25mhz), GLOBAL(reset), , , , );


--count_x[9] is count_x[9] at LC_X12_Y11_N3
--operation mode is normal

count_x[9]_lut_out = !A1L741 & A1L25;
count_x[9] = DFFEA(count_x[9]_lut_out, GLOBAL(clock_25mhz), GLOBAL(reset), , , , );


--count_y[8] is count_y[8] at LC_X15_Y10_N9
--operation mode is normal

count_y[8]_lut_out = A1L58 & (!count_y[1] # !A1L341 # !A1L441);
count_y[8] = DFFEA(count_y[8]_lut_out, GLOBAL(clock_25mhz), GLOBAL(reset), , A1L741, , );


--count_y[7] is count_y[7] at LC_X15_Y10_N0
--operation mode is normal

count_y[7]_lut_out = A1L18 & (!count_y[1] # !A1L341 # !A1L441);
count_y[7] = DFFEA(count_y[7]_lut_out, GLOBAL(clock_25mhz), GLOBAL(reset), , A1L741, , );


--count_y[6] is count_y[6] at LC_X15_Y10_N3
--operation mode is normal

count_y[6]_lut_out = A1L77 & (!count_y[1] # !A1L341 # !A1L441);
count_y[6] = DFFEA(count_y[6]_lut_out, GLOBAL(clock_25mhz), GLOBAL(reset), , A1L741, , );


--count_y[5] is count_y[5] at LC_X15_Y10_N8
--operation mode is normal

count_y[5]_lut_out = A1L37 & (!count_y[1] # !A1L341 # !A1L441);
count_y[5] = DFFEA(count_y[5]_lut_out, GLOBAL(clock_25mhz), GLOBAL(reset), , A1L741, , );


--A1L441 is reduce_nor~108 at LC_X15_Y10_N1
--operation mode is normal

A1L441 = count_y[8] & count_y[6] & count_y[5] & count_y[7];


--D1_ram_block1a1 is tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|ram_block1a1 at M4K_X13_Y10
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 16384, Port A Logical Width: 1
--Port A Input: Registered, Port A Output: Un-registered
D1_ram_block1a1_PORT_A_address = BUS(address[0], address[1], address[2], address[3], address[4], address[5], address[6], address[7], address[8], address[9], address[10], address[11]);
D1_ram_block1a1_PORT_A_address_reg = DFFE(D1_ram_block1a1_PORT_A_address, D1_ram_block1a1_clock_0, , , );
D1_ram_block1a1_clock_0 = GLOBAL(clock0);
D1_ram_block1a1_PORT_A_data_out = MEMORY(, , D1_ram_block1a1_PORT_A_address_reg, , , , , , D1_ram_block1a1_clock_0, , , , , );
D1_ram_block1a1 = D1_ram_block1a1_PORT_A_data_out[0];


--D1_ram_block1a2 is tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|ram_block1a2 at M4K_X13_Y13
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 16384, Port A Logical Width: 1
--Port A Input: Registered, Port A Output: Un-registered
D1_ram_block1a2_PORT_A_address = BUS(address[0], address[1], address[2], address[3], address[4], address[5], address[6], address[7], address[8], address[9], address[10], address[11]);
D1_ram_block1a2_PORT_A_address_reg = DFFE(D1_ram_block1a2_PORT_A_address, D1_ram_block1a2_clock_0, , , );
D1_ram_block1a2_clock_0 = GLOBAL(clock0);
D1_ram_block1a2_PORT_A_data_out = MEMORY(, , D1_ram_block1a2_PORT_A_address_reg, , , , , , D1_ram_block1a2_clock_0, , , , , );
D1_ram_block1a2 = D1_ram_block1a2_PORT_A_data_out[0];


--D1_ram_block1a0 is tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|ram_block1a0 at M4K_X13_Y11
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 16384, Port A Logical Width: 1
--Port A Input: Registered, Port A Output: Un-registered
D1_ram_block1a0_PORT_A_address = BUS(address[0], address[1], address[2], address[3], address[4], address[5], address[6], address[7], address[8], address[9], address[10], address[11]);
D1_ram_block1a0_PORT_A_address_reg = DFFE(D1_ram_block1a0_PORT_A_address, D1_ram_block1a0_clock_0, , , );
D1_ram_block1a0_clock_0 = GLOBAL(clock0);
D1_ram_block1a0_PORT_A_data_out = MEMORY(, , D1_ram_block1a0_PORT_A_address_reg, , , , , , D1_ram_block1a0_clock_0, , , , , );
D1_ram_block1a0 = D1_ram_block1a0_PORT_A_data_out[0];


--E1L1 is tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|mux_rab:mux2|w_result37w~37 at LC_X12_Y10_N1
--operation mode is normal

D1_address_reg_a[1]_qfbk = D1_address_reg_a[1];
E1L1 = D1_address_reg_a[1]_qfbk & (D1_address_reg_a[0] # D1_ram_block1a2) # !D1_address_reg_a[1]_qfbk & !D1_address_reg_a[0] & D1_ram_block1a0;

--D1_address_reg_a[1] is tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|address_reg_a[1] at LC_X12_Y10_N1
--operation mode is normal

D1_address_reg_a[1]_sload_eqn = address[13];
D1_address_reg_a[1] = DFFEA(D1_address_reg_a[1]_sload_eqn, GLOBAL(clock0), VCC, , , , );


--D1_ram_block1a3 is tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|ram_block1a3 at M4K_X13_Y12
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 16384, Port A Logical Width: 1
--Port A Input: Registered, Port A Output: Un-registered
D1_ram_block1a3_PORT_A_address = BUS(address[0], address[1], address[2], address[3], address[4], address[5], address[6], address[7], address[8], address[9], address[10], address[11]);
D1_ram_block1a3_PORT_A_address_reg = DFFE(D1_ram_block1a3_PORT_A_address, D1_ram_block1a3_clock_0, , , );
D1_ram_block1a3_clock_0 = GLOBAL(clock0);
D1_ram_block1a3_PORT_A_data_out = MEMORY(, , D1_ram_block1a3_PORT_A_address_reg, , , , , , D1_ram_block1a3_clock_0, , , , , );
D1_ram_block1a3 = D1_ram_block1a3_PORT_A_data_out[0];


--E1L2 is tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|mux_rab:mux2|w_result37w~38 at LC_X12_Y10_N2
--operation mode is normal

D1_address_reg_a[0]_qfbk = D1_address_reg_a[0];
E1L2 = E1L1 & (D1_ram_block1a3 # !D1_address_reg_a[0]_qfbk) # !E1L1 & D1_ram_block1a1 & D1_address_reg_a[0]_qfbk;

--D1_address_reg_a[0] is tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|address_reg_a[0] at LC_X12_Y10_N2
--operation mode is normal

D1_address_reg_a[0]_sload_eqn = address[12];
D1_address_reg_a[0] = DFFEA(D1_address_reg_a[0]_sload_eqn, GLOBAL(clock0), VCC, , , , );


--count_z[2] is count_z[2] at LC_X10_Y10_N1
--operation mode is normal

count_z[2]_lut_out = A1L49 & (count_z[1] # !count_z[4] # !A1L241);
count_z[2] = DFFEA(count_z[2]_lut_out, GLOBAL(clock2), GLOBAL(reset), , , , );


--count_z[1] is count_z[1] at LC_X10_Y10_N4
--operation mode is normal

count_z[1]_lut_out = A1L09 & (count_z[1] # !count_z[4] # !A1L241);
count_z[1] = DFFEA(count_z[1]_lut_out, GLOBAL(clock2), GLOBAL(reset), , , , );


--A1L921 is count_z[0]~187 at LC_X11_Y10_N6
--operation mode is normal

A1L921 = !count_z[0] & !count_z[1];


--count_z[4] is count_z[4] at LC_X10_Y10_N3
--operation mode is normal

count_z[4]_lut_out = A1L201 & (count_z[1] # !A1L241 # !count_z[4]);
count_z[4] = DFFEA(count_z[4]_lut_out, GLOBAL(clock2), GLOBAL(reset), , , , );


--A1L631 is process10~351 at LC_X10_Y10_N0
--operation mode is normal

count_z[3]_qfbk = count_z[3];
A1L631 = !count_z[3]_qfbk & !count_z[4];

--count_z[3] is count_z[3] at LC_X10_Y10_N0
--operation mode is normal

count_z[3]_sload_eqn = A1L89;
count_z[3] = DFFEA(count_z[3]_sload_eqn, GLOBAL(clock2), GLOBAL(reset), , , , );


--A1L561 is vga_read~96 at LC_X12_Y10_N3
--operation mode is normal

A1L561 = E1L2 & (A1L921 # count_z[2] # !A1L631);


--A1L731 is process10~352 at LC_X11_Y10_N5
--operation mode is normal

A1L731 = count_z[2] & count_z[1] & !count_z[3] & count_z[0] # !count_z[2] & !count_z[1] & count_z[3];


--A1L431 is process10~78 at LC_X11_Y10_N4
--operation mode is normal

A1L431 = !count_z[1] # !count_z[0];


--A1L831 is process10~353 at LC_X15_Y11_N1
--operation mode is normal

count_x[7]_qfbk = count_x[7];
A1L831 = count_x[9] # count_x[8] $ (!count_x[6] # !count_x[7]_qfbk);

--count_x[7] is count_x[7] at LC_X15_Y11_N1
--operation mode is normal

count_x[7]_sload_eqn = A1L44;
count_x[7] = DFFEA(count_x[7]_sload_eqn, GLOBAL(clock_25mhz), GLOBAL(reset), , , , );


--count_x[5] is count_x[5] at LC_X12_Y11_N7
--operation mode is normal

count_x[5]_lut_out = A1L63 & !A1L741;
count_x[5] = DFFEA(count_x[5]_lut_out, GLOBAL(clock_25mhz), GLOBAL(reset), , , , );


--A1L931 is process10~354 at LC_X15_Y11_N0
--operation mode is normal

count_x[4]_qfbk = count_x[4];
A1L931 = !count_x[8] & !count_x[5] & !count_x[4]_qfbk & !count_x[3];

--count_x[4] is count_x[4] at LC_X15_Y11_N0
--operation mode is normal

count_x[4]_sload_eqn = A1L43;
count_x[4] = DFFEA(count_x[4]_sload_eqn, GLOBAL(clock_25mhz), GLOBAL(reset), , , , );


--count_x[0] is count_x[0] at LC_X12_Y11_N9
--operation mode is normal

count_x[0]_sload_eqn = A1L81;
count_x[0] = DFFEA(count_x[0]_sload_eqn, GLOBAL(clock_25mhz), GLOBAL(reset), , , , );


--A1L041 is process10~355 at LC_X15_Y11_N7
--operation mode is normal

count_x[1]_qfbk = count_x[1];
A1L041 = !count_x[1]_qfbk & !count_x[0];

--count_x[1] is count_x[1] at LC_X15_Y11_N7
--operation mode is normal

count_x[1]_sload_eqn = A1L22;
count_x[1] = DFFEA(count_x[1]_sload_eqn, GLOBAL(clock_25mhz), GLOBAL(reset), , , , );


--A1L141 is process10~356 at LC_X15_Y11_N8
--operation mode is normal

count_x[2]_qfbk = count_x[2];
A1L141 = !A1L831 & (count_x[2]_qfbk # !A1L041 # !A1L931);

--count_x[2] is count_x[2] at LC_X15_Y11_N8
--operation mode is normal

count_x[2]_sload_eqn = A1L62;
count_x[2] = DFFEA(count_x[2]_sload_eqn, GLOBAL(clock_25mhz), GLOBAL(reset), , , , );


--A1L851 is vga_green~107 at LC_X11_Y10_N9
--operation mode is normal

A1L851 = count_z[3] & (count_z[2] # count_z[1]);


--A1L251 is vga_blue~511 at LC_X12_Y10_N6
--operation mode is normal

A1L251 = count_z[4] & (count_z[3] # count_z[2] # !A1L431);


--A1L351 is vga_blue~512 at LC_X12_Y10_N7
--operation mode is normal

A1L351 = A1L251 # A1L631 & !count_z[2] & !A1L921;


--A1L451 is vga_blue~513 at LC_X12_Y10_N8
--operation mode is normal

A1L451 = !count_z[4] & (!A1L921 & count_z[2] # !A1L851);


--A1L84 is add~34 at LC_X16_Y11_N8
--operation mode is arithmetic

A1L84_carry_eqn = (!A1L53 & A1L64) # (A1L53 & A1L74);
A1L84 = count_x[8] $ !A1L84_carry_eqn;

--A1L05 is add~34COUT0 at LC_X16_Y11_N8
--operation mode is arithmetic

A1L05_cout_0 = count_x[8] & !A1L64;
A1L05 = CARRY(A1L05_cout_0);

--A1L15 is add~34COUT1 at LC_X16_Y11_N8
--operation mode is arithmetic

A1L15_cout_1 = count_x[8] & !A1L74;
A1L15 = CARRY(A1L15_cout_1);


--A1L541 is reduce_nor~109 at LC_X12_Y11_N4
--operation mode is normal

A1L541 = count_x[5] # count_x[7] # !count_x[8] # !count_x[9];


--A1L641 is reduce_nor~110 at LC_X12_Y11_N5
--operation mode is normal

count_x[3]_qfbk = count_x[3];
A1L641 = !count_x[2] # !count_x[3]_qfbk # !count_x[1] # !count_x[4];

--count_x[3] is count_x[3] at LC_X12_Y11_N5
--operation mode is normal

count_x[3]_sload_eqn = A1L03;
count_x[3] = DFFEA(count_x[3]_sload_eqn, GLOBAL(clock_25mhz), GLOBAL(reset), , , , );


--A1L741 is reduce_nor~111 at LC_X12_Y11_N6
--operation mode is normal

count_x[6]_qfbk = count_x[6];
A1L741 = count_x[0] & !A1L541 & !count_x[6]_qfbk & !A1L641;

--count_x[6] is count_x[6] at LC_X12_Y11_N6
--operation mode is normal

count_x[6]_sload_eqn = A1L04;
count_x[6] = DFFEA(count_x[6]_sload_eqn, GLOBAL(clock_25mhz), GLOBAL(reset), , , , );


--A1L44 is add~33 at LC_X16_Y11_N7
--operation mode is arithmetic

A1L44_carry_eqn = (!A1L53 & A1L24) # (A1L53 & A1L34);
A1L44 = count_x[7] $ A1L44_carry_eqn;

--A1L64 is add~33COUT0 at LC_X16_Y11_N7
--operation mode is arithmetic

A1L64_cout_0 = !A1L24 # !count_x[7];
A1L64 = CARRY(A1L64_cout_0);

--A1L74 is add~33COUT1 at LC_X16_Y11_N7
--operation mode is arithmetic

A1L74_cout_1 = !A1L34 # !count_x[7];
A1L74 = CARRY(A1L74_cout_1);


--A1L25 is add~35 at LC_X16_Y11_N9
--operation mode is normal

A1L25_carry_eqn = (!A1L53 & A1L05) # (A1L53 & A1L15);
A1L25 = A1L25_carry_eqn $ count_x[9];


--A1L58 is add~44 at LC_X15_Y9_N8
--operation mode is normal

A1L58_carry_eqn = (!A1L07 & A1L38) # (A1L07 & A1L48);
A1L58 = A1L58_carry_eqn $ !count_y[8];


--count_y[1] is count_y[1] at LC_X15_Y9_N9
--operation mode is normal

count_y[1]_lut_out = A1L75 & (!A1L341 # !A1L441 # !count_y[1]);
count_y[1] = DFFEA(count_y[1]_lut_out, GLOBAL(clock_25mhz), GLOBAL(reset), , A1L741, , );


--count_y[3] is count_y[3] at LC_X15_Y11_N6
--operation mode is normal

count_y[3]_lut_out = A1L56;
count_y[3] = DFFEA(count_y[3]_lut_out, GLOBAL(clock_25mhz), GLOBAL(reset), , A1L741, , );


--count_y[2] is count_y[2] at LC_X15_Y11_N5
--operation mode is normal

count_y[2]_sload_eqn = A1L16;
count_y[2] = DFFEA(count_y[2]_sload_eqn, GLOBAL(clock_25mhz), GLOBAL(reset), , A1L741, , );


--count_y[0] is count_y[0] at LC_X15_Y10_N2
--operation mode is normal

count_y[0]_lut_out = A1L35 & (!count_y[1] # !A1L341 # !A1L441);
count_y[0] = DFFEA(count_y[0]_lut_out, GLOBAL(clock_25mhz), GLOBAL(reset), , A1L741, , );


--A1L341 is process11~63 at LC_X15_Y11_N2
--operation mode is normal

count_y[4]_qfbk = count_y[4];
A1L341 = !count_y[0] & !count_y[2] & !count_y[4]_qfbk & !count_y[3];

--count_y[4] is count_y[4] at LC_X15_Y11_N2
--operation mode is normal

count_y[4]_sload_eqn = A1L96;
count_y[4] = DFFEA(count_y[4]_sload_eqn, GLOBAL(clock_25mhz), GLOBAL(reset), , A1L741, , );


--A1L18 is add~43 at LC_X15_Y9_N7
--operation mode is arithmetic

A1L18_carry_eqn = (!A1L07 & A1L97) # (A1L07 & A1L08);
A1L18 = count_y[7] $ A1L18_carry_eqn;

--A1L38 is add~43COUT0 at LC_X15_Y9_N7
--operation mode is arithmetic

A1L38_cout_0 = !A1L97 # !count_y[7];
A1L38 = CARRY(A1L38_cout_0);

--A1L48 is add~43COUT1 at LC_X15_Y9_N7
--operation mode is arithmetic

A1L48_cout_1 = !A1L08 # !count_y[7];
A1L48 = CARRY(A1L48_cout_1);


--A1L77 is add~42 at LC_X15_Y9_N6
--operation mode is arithmetic

A1L77_carry_eqn = (!A1L07 & A1L57) # (A1L07 & A1L67);
A1L77 = count_y[6] $ !A1L77_carry_eqn;