📄 vgainterface.fit.rpt
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+----------------------------+-----------------------+
; Interconnect Resource Type ; Usage ;
+----------------------------+-----------------------+
; C4s ; 81 / 8,840 ( < 1 % ) ;
; Direct links ; 25 / 11,506 ( < 1 % ) ;
; Global clocks ; 4 / 8 ( 50 % ) ;
; LAB clocks ; 22 / 156 ( 14 % ) ;
; LUT chains ; 9 / 2,619 ( < 1 % ) ;
; Local interconnects ; 158 / 11,506 ( 1 % ) ;
; M4K buffers ; 4 / 468 ( < 1 % ) ;
; R4s ; 63 / 7,520 ( < 1 % ) ;
+----------------------------+-----------------------+
+---------------------------------------------------------------------------+
; LAB Logic Elements ;
+--------------------------------------------+------------------------------+
; Number of Logic Elements (Average = 8.00) ; Number of LABs (Total = 11) ;
+--------------------------------------------+------------------------------+
; 1 ; 1 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 1 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 2 ;
; 8 ; 0 ;
; 9 ; 1 ;
; 10 ; 6 ;
+--------------------------------------------+------------------------------+
+-------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+------------------------------+
; LAB-wide Signals (Average = 2.09) ; Number of LABs (Total = 11) ;
+------------------------------------+------------------------------+
; 1 Async. clear ; 9 ;
; 1 Clock ; 8 ;
; 1 Clock enable ; 4 ;
; 2 Clock enables ; 1 ;
; 2 Clocks ; 1 ;
+------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Signals Sourced ;
+---------------------------------------------+------------------------------+
; Number of Signals Sourced (Average = 8.91) ; Number of LABs (Total = 11) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 1 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 1 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 2 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 3 ;
; 11 ; 2 ;
; 12 ; 1 ;
; 13 ; 0 ;
; 14 ; 0 ;
; 15 ; 1 ;
+---------------------------------------------+------------------------------+
+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+------------------------------+
; Number of Signals Sourced Out (Average = 6.82) ; Number of LABs (Total = 11) ;
+-------------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 1 ;
; 2 ; 0 ;
; 3 ; 1 ;
; 4 ; 1 ;
; 5 ; 1 ;
; 6 ; 1 ;
; 7 ; 1 ;
; 8 ; 0 ;
; 9 ; 2 ;
; 10 ; 2 ;
; 11 ; 1 ;
+-------------------------------------------------+------------------------------+
+-----------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+----------------------------------------------+------------------------------+
; Number of Distinct Inputs (Average = 10.36) ; Number of LABs (Total = 11) ;
+----------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 2 ;
; 3 ; 0 ;
; 4 ; 1 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 1 ;
; 10 ; 2 ;
; 11 ; 1 ;
; 12 ; 0 ;
; 13 ; 2 ;
; 14 ; 0 ;
; 15 ; 0 ;
; 16 ; 0 ;
; 17 ; 0 ;
; 18 ; 1 ;
; 19 ; 0 ;
; 20 ; 0 ;
; 21 ; 0 ;
; 22 ; 1 ;
+----------------------------------------------+------------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
Info: Processing started: Tue Apr 26 12:19:41 2005
Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off vgainterface -c vgainterface
Info: Selected device EP1C3T144C6 for design vgainterface
Info: Fitter is performing an Auto Fit compilation -- Fitter effort may be decreased to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices.
Info: Device EP1C6T144C6 is compatible
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
Info: Assuming a global fmax requirement of 1 MHz
Info: Not setting a global tsu requirement
Info: Not setting a global tco requirement
Info: Not setting a global tpd requirement
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted some destinations of signal clock_25mhz to use Global cloc
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