📄 ps2.map.rpt
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; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 0 ;
; -- asynchronous clear/load mode ; 1 ;
; ; ;
; Total registers ; 41 ;
; Total logic cells in carry chains ; 20 ;
; I/O pins ; 9 ;
; Total memory bits ; 1792 ;
; Maximum fan-out node ; CLK ;
; Maximum fan-out ; 27 ;
; Total fan-out ; 486 ;
; Average fan-out ; 3.24 ;
+---------------------------------------------+-------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+---------------------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------------------------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; M4Ks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+---------------------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------------------------------------------+
; |PS2 ; 134 (21) ; 41 ; 1792 ; 0 ; 9 ; 0 ; 93 (0) ; 28 (20) ; 13 (1) ; 20 (0) ; 0 (0) ; |PS2 ;
; |altsyncram:Mux6_rtl_0| ; 0 (0) ; 0 ; 1792 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |PS2|altsyncram:Mux6_rtl_0 ;
; |altsyncram_pvt:auto_generated| ; 0 (0) ; 0 ; 1792 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |PS2|altsyncram:Mux6_rtl_0|altsyncram_pvt:auto_generated ;
; |vga_16:U2| ; 113 (113) ; 20 ; 0 ; 0 ; 0 ; 0 ; 93 (93) ; 8 (8) ; 12 (12) ; 20 (20) ; 0 (0) ; |PS2|vga_16:U2 ;
+---------------------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ;
+----------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+------+--------------+
; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
+----------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+------+--------------+
; altsyncram:Mux6_rtl_0|altsyncram_pvt:auto_generated|ALTSYNCRAM ; AUTO ; ROM ; 256 ; 7 ; -- ; -- ; 1792 ; PS20.rtl.mif ;
+----------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+------+--------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 41 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 1 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+--------------------------------------------------+
; Inverted Register Statistics ;
+----------------------------------------+---------+
; Inverted Register ; Fan out ;
+----------------------------------------+---------+
; CLK ; 27 ;
; Total number of inverted registers = 1 ; ;
+----------------------------------------+---------+
+----------------------------------------------------------------------------+
; Source assignments for altsyncram:Mux6_rtl_0|altsyncram_pvt:auto_generated ;
+---------------------------------+--------------------+------+--------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+--------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+--------------+
+------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: altsyncram:Mux6_rtl_0 ;
+------------------------------------+----------------+------------------+
; Parameter Name ; Value ; Type ;
+------------------------------------+----------------+------------------+
; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; OPERATION_MODE ; ROM ; Untyped ;
; WIDTH_A ; 7 ; Untyped ;
; WIDTHAD_A ; 8 ; Untyped ;
; NUMWORDS_A ; 256 ; Untyped ;
; OUTDATA_REG_A ; UNREGISTERED ; Untyped ;
; ADDRESS_ACLR_A ; NONE ; Untyped ;
; OUTDATA_ACLR_A ; NONE ; Untyped ;
; WRCONTROL_ACLR_A ; NONE ; Untyped ;
; INDATA_ACLR_A ; NONE ; Untyped ;
; BYTEENA_ACLR_A ; NONE ; Untyped ;
; WIDTH_B ; 1 ; Untyped ;
; WIDTHAD_B ; 1 ; Untyped ;
; NUMWORDS_B ; 1 ; Untyped ;
; INDATA_REG_B ; CLOCK1 ; Untyped ;
; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
; ADDRESS_REG_B ; CLOCK1 ; Untyped ;
; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
; INDATA_ACLR_B ; NONE ; Untyped ;
; WRCONTROL_ACLR_B ; NONE ; Untyped ;
; ADDRESS_ACLR_B ; NONE ; Untyped ;
; OUTDATA_ACLR_B ; NONE ; Untyped ;
; RDCONTROL_ACLR_B ; NONE ; Untyped ;
; BYTEENA_ACLR_B ; NONE ; Untyped ;
; WIDTH_BYTEENA_A ; 1 ; Untyped ;
; WIDTH_BYTEENA_B ; 1 ; Untyped ;
; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
; BYTE_SIZE ; 8 ; Untyped ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;
; INIT_FILE ; PS20.rtl.mif ; Untyped ;
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
; MAXIMUM_DEPTH ; 0 ; Untyped ;
; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
; DEVICE_FAMILY ; Cyclone ; Untyped ;
; CBXI_PARAMETER ; altsyncram_pvt ; Untyped ;
+------------------------------------+----------------+------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
Info: Processing started: Fri Aug 17 17:56:22 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ps2 -c ps2
Info: Found 2 design units, including 1 entities, in source file vga_16.vhd
Info: Found design unit 1: vga_16-Behavioral
Info: Found entity 1: vga_16
Warning: Using design file ps2.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: PS2-PS2_arch
Info: Found entity 1: PS2
Info: Elaborating entity "ps2" for the top level hierarchy
Info: Elaborating entity "vga_16" for hierarchy "vga_16:U2"
Warning: Created node "Mux6~255" as a ROM by generating altsyncram megafunction to implement register logic with M512 or M4K memory block. Power-up state differs from the original design.
Info: Inferred 1 megafunctions from design logic
Info: Inferred altsyncram megafunction (OPERATION_MODE=ROM, NUMWORDS_A=256, WIDTH_A=7) from the following design logic: "Mux6~255"
Info: Found 1 design units, including 1 entities, in source file ../../libraries/megafunctions/altsyncram.tdf
Info: Found entity 1: altsyncram
Info: Elaborated megafunction instantiation "altsyncram:Mux6_rtl_0"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_pvt.tdf
Info: Found entity 1: altsyncram_pvt
Info: Registers with preset signals will power-up high
Info: Implemented 150 device resources after synthesis - the final resource count might be different
Info: Implemented 4 input pins
Info: Implemented 5 output pins
Info: Implemented 134 logic cells
Info: Implemented 7 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
Info: Processing ended: Fri Aug 17 17:56:29 2007
Info: Elapsed time: 00:00:08
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