ps2.fit.qmsg

用键盘控制FPGA

{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0 0 "Finished moving registers into I/O cells, LUTs, and RAM blocks" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.941 ns register register " "Info: Estimated most critical path is register to register delay of 3.941 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vga_16:U2\|ll\[0\] 1 REG LAB_X23_Y15 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X23_Y15; Fanout = 7; REG Node = 'vga_16:U2\|ll\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { vga_16:U2|ll[0] } "NODE_NAME" } } { "vga_16.vhd" "" { Text "D:/altera/quartus60/program/ps2/vga_16.vhd" 64 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.148 ns) + CELL(0.575 ns) 1.723 ns vga_16:U2\|Add2~149COUT1_151 2 COMB LAB_X24_Y14 2 " "Info: 2: + IC(1.148 ns) + CELL(0.575 ns) = 1.723 ns; Loc. = LAB_X24_Y14; Fanout = 2; COMB Node = 'vga_16:U2\|Add2~149COUT1_151'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.723 ns" { vga_16:U2|ll[0] vga_16:U2|Add2~149COUT1_151 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.803 ns vga_16:U2\|Add2~147COUT1_152 3 COMB LAB_X24_Y14 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.803 ns; Loc. = LAB_X24_Y14; Fanout = 2; COMB Node = 'vga_16:U2\|Add2~147COUT1_152'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.080 ns" { vga_16:U2|Add2~149COUT1_151 vga_16:U2|Add2~147COUT1_152 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.883 ns vga_16:U2\|Add2~145COUT1_153 4 COMB LAB_X24_Y14 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.883 ns; Loc. = LAB_X24_Y14; Fanout = 2; COMB Node = 'vga_16:U2\|Add2~145COUT1_153'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.080 ns" { vga_16:U2|Add2~147COUT1_152 vga_16:U2|Add2~145COUT1_153 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.963 ns vga_16:U2\|Add2~143COUT1 5 COMB LAB_X24_Y14 2 " "Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 1.963 ns; Loc. = LAB_X24_Y14; Fanout = 2; COMB Node = 'vga_16:U2\|Add2~143COUT1'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.080 ns" { vga_16:U2|Add2~145COUT1_153 vga_16:U2|Add2~143COUT1 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.258 ns) 2.221 ns vga_16:U2\|Add2~141 6 COMB LAB_X24_Y14 4 " "Info: 6: + IC(0.000 ns) + CELL(0.258 ns) = 2.221 ns; Loc. = LAB_X24_Y14; Fanout = 4; COMB Node = 'vga_16:U2\|Add2~141'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.258 ns" { vga_16:U2|Add2~143COUT1 vga_16:U2|Add2~141 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.679 ns) 2.900 ns vga_16:U2\|Add2~132 7 COMB LAB_X24_Y14 1 " "Info: 7: + IC(0.000 ns) + CELL(0.679 ns) = 2.900 ns; Loc. = LAB_X24_Y14; Fanout = 1; COMB Node = 'vga_16:U2\|Add2~132'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.679 ns" { vga_16:U2|Add2~141 vga_16:U2|Add2~132 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.303 ns) + CELL(0.738 ns) 3.941 ns vga_16:U2\|ll\[8\] 8 REG LAB_X23_Y14 9 " "Info: 8: + IC(0.303 ns) + CELL(0.738 ns) = 3.941 ns; Loc. = LAB_X23_Y14; Fanout = 9; REG Node = 'vga_16:U2\|ll\[8\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.041 ns" { vga_16:U2|Add2~132 vga_16:U2|ll[8] } "NODE_NAME" } } { "vga_16.vhd" "" { Text "D:/altera/quartus60/program/ps2/vga_16.vhd" 64 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.490 ns ( 63.18 % ) " "Info: Total cell delay = 2.490 ns ( 63.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.451 ns ( 36.82 % ) " "Info: Total interconnect delay = 1.451 ns ( 36.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.941 ns" { vga_16:U2|ll[0] vga_16:U2|Add2~149COUT1_151 vga_16:U2|Add2~147COUT1_152 vga_16:U2|Add2~145COUT1_153 vga_16:U2|Add2~143COUT1 vga_16:U2|Add2~141 vga_16:U2|Add2~132 vga_16:U2|ll[8] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 1 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 1%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "x21_y14 x31_y27 " "Info: The peak interconnect region extends from location x21_y14 to location x31_y27" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Aug 17 17:56:45 2007 " "Info: Processing ended: Fri Aug 17 17:56:45 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Info: Elapsed time: 00:00:13" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/altera/quartus60/program/ps2/ps2.fit.smsg " "Info: Generated suppressed messages file D:/altera/quartus60/program/ps2/ps2.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}