count_top.map.qmsg

用键盘控制FPGA

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version " "Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Aug 17 17:43:34 2007 " "Info: Processing started: Fri Aug 17 17:43:34 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off count_top -c count_top " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off count_top -c count_top" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "count_top.vhd 8 4 " "Warning: Using design file count_top.vhd, which is not specified as a design file for the current project, but contains definitions for 8 design units and 4 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 count_top-Behavioral " "Info: Found design unit 1: count_top-Behavioral" {  } { { "count_top.vhd" "" { Text "D:/altera/quartus60/program/ps2/count_top.vhd" 18 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 counter-Behavioral " "Info: Found design unit 2: counter-Behavioral" {  } { { "count_top.vhd" "" { Text "D:/altera/quartus60/program/ps2/count_top.vhd" 93 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 HEX2LED_4-Behavioral " "Info: Found design unit 3: HEX2LED_4-Behavioral" {  } { { "count_top.vhd" "" { Text "D:/altera/quartus60/program/ps2/count_top.vhd" 126 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "4 vga_16-Behavioral " "Info: Found design unit 4: vga_16-Behavioral" {  } { { "count_top.vhd" "" { Text "D:/altera/quartus60/program/ps2/count_top.vhd" 230 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 count_top " "Info: Found entity 1: count_top" {  } { { "count_top.vhd" "" { Text "D:/altera/quartus60/program/ps2/count_top.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 counter " "Info: Found entity 2: counter" {  } { { "count_top.vhd" "" { Text "D:/altera/quartus60/program/ps2/count_top.vhd" 86 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "3 HEX2LED_4 " "Info: Found entity 3: HEX2LED_4" {  } { { "count_top.vhd" "" { Text "D:/altera/quartus60/program/ps2/count_top.vhd" 119 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "4 vga_16 " "Info: Found entity 4: vga_16" {  } { { "count_top.vhd" "" { Text "D:/altera/quartus60/program/ps2/count_top.vhd" 216 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "count_top " "Info: Elaborating entity \"count_top\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter counter:U1 " "Info: Elaborating entity \"counter\" for hierarchy \"counter:U1\"" {  } { { "count_top.vhd" "U1" { Text "D:/altera/quartus60/program/ps2/count_top.vhd" 69 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "HEX2LED_4 HEX2LED_4:U2 " "Info: Elaborating entity \"HEX2LED_4\" for hierarchy \"HEX2LED_4:U2\"" {  } { { "count_top.vhd" "U2" { Text "D:/altera/quartus60/program/ps2/count_top.vhd" 70 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "vga_16 vga_16:U3 " "Info: Elaborating entity \"vga_16\" for hierarchy \"vga_16:U3\"" {  } { { "count_top.vhd" "U3" { Text "D:/altera/quartus60/program/ps2/count_top.vhd" 71 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "212 " "Info: Implemented 212 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "4 " "Info: Implemented 4 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "10 " "Info: Implemented 10 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "198 " "Info: Implemented 198 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Aug 17 17:43:44 2007 " "Info: Processing ended: Fri Aug 17 17:43:44 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Info: Elapsed time: 00:00:11" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}