ps2.tan.qmsg

用键盘控制FPGA

{ "Info" "ITDB_TH_RESULT" "M\[9\] KBdata CLKIN -1.378 ns register " "Info: th for register \"M\[9\]\" (data pin = \"KBdata\", clock pin = \"CLKIN\") is -1.378 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLKIN destination 7.754 ns + Longest register " "Info: + Longest clock path from clock \"CLKIN\" to destination register is 7.754 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLKIN 1 CLK PIN_153 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 7; CLK Node = 'CLKIN'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLKIN } "NODE_NAME" } } { "ps2.vhd" "" { Text "D:/altera/quartus60/program/ps2/ps2.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.935 ns) 3.435 ns CLK 2 REG LC_X8_Y13_N2 28 " "Info: 2: + IC(1.031 ns) + CELL(0.935 ns) = 3.435 ns; Loc. = LC_X8_Y13_N2; Fanout = 28; REG Node = 'CLK'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.966 ns" { CLKIN CLK } "NODE_NAME" } } { "ps2.vhd" "" { Text "D:/altera/quartus60/program/ps2/ps2.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.608 ns) + CELL(0.711 ns) 7.754 ns M\[9\] 3 REG LC_X18_Y14_N3 1 " "Info: 3: + IC(3.608 ns) + CELL(0.711 ns) = 7.754 ns; Loc. = LC_X18_Y14_N3; Fanout = 1; REG Node = 'M\[9\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.319 ns" { CLK M[9] } "NODE_NAME" } } { "ps2.vhd" "" { Text "D:/altera/quartus60/program/ps2/ps2.vhd" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 40.17 % ) " "Info: Total cell delay = 3.115 ns ( 40.17 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.639 ns ( 59.83 % ) " "Info: Total interconnect delay = 4.639 ns ( 59.83 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.754 ns" { CLKIN CLK M[9] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.754 ns" { CLKIN CLKIN~out0 CLK M[9] } { 0.000ns 0.000ns 1.031ns 3.608ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "ps2.vhd" "" { Text "D:/altera/quartus60/program/ps2/ps2.vhd" 59 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.147 ns - Shortest pin register " "Info: - Shortest pin to register delay is 9.147 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns KBdata 1 PIN PIN_1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_1; Fanout = 1; PIN Node = 'KBdata'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { KBdata } "NODE_NAME" } } { "ps2.vhd" "" { Text "D:/altera/quartus60/program/ps2/ps2.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.563 ns) + CELL(0.115 ns) 9.147 ns M\[9\] 2 REG LC_X18_Y14_N3 1 " "Info: 2: + IC(7.563 ns) + CELL(0.115 ns) = 9.147 ns; Loc. = LC_X18_Y14_N3; Fanout = 1; REG Node = 'M\[9\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.678 ns" { KBdata M[9] } "NODE_NAME" } } { "ps2.vhd" "" { Text "D:/altera/quartus60/program/ps2/ps2.vhd" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.584 ns ( 17.32 % ) " "Info: Total cell delay = 1.584 ns ( 17.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.563 ns ( 82.68 % ) " "Info: Total interconnect delay = 7.563 ns ( 82.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.147 ns" { KBdata M[9] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "9.147 ns" { KBdata KBdata~out0 M[9] } { 0.000ns 0.000ns 7.563ns } { 0.000ns 1.469ns 0.115ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.754 ns" { CLKIN CLK M[9] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.754 ns" { CLKIN CLKIN~out0 CLK M[9] } { 0.000ns 0.000ns 1.031ns 3.608ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.147 ns" { KBdata M[9] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "9.147 ns" { KBdata KBdata~out0 M[9] } { 0.000ns 0.000ns 7.563ns } { 0.000ns 1.469ns 0.115ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Aug 17 17:56:55 2007 " "Info: Processing ended: Fri Aug 17 17:56:55 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}