ps2.tan.qmsg

用键盘控制FPGA

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "3 " "Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "CLK " "Info: Detected ripple clock \"CLK\" as buffer" {  } { { "ps2.vhd" "" { Text "D:/altera/quartus60/program/ps2/ps2.vhd" 36 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "vga_16:U2\|fs\[5\] " "Info: Detected ripple clock \"vga_16:U2\|fs\[5\]\" as buffer" {  } { { "vga_16.vhd" "" { Text "D:/altera/quartus60/program/ps2/vga_16.vhd" 26 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "vga_16:U2\|fs\[5\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "vga_16:U2\|cc\[4\] " "Info: Detected ripple clock \"vga_16:U2\|cc\[4\]\" as buffer" {  } { { "vga_16.vhd" "" { Text "D:/altera/quartus60/program/ps2/vga_16.vhd" 54 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "vga_16:U2\|cc\[4\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLKIN register vga_16:U2\|cc\[4\] register vga_16:U2\|cc\[2\] 229.41 MHz 4.359 ns Internal " "Info: Clock \"CLKIN\" has Internal fmax of 229.41 MHz between source register \"vga_16:U2\|cc\[4\]\" and destination register \"vga_16:U2\|cc\[2\]\" (period= 4.359 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.098 ns + Longest register register " "Info: + Longest register to register delay is 4.098 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vga_16:U2\|cc\[4\] 1 REG LC_X15_Y13_N7 20 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X15_Y13_N7; Fanout = 20; REG Node = 'vga_16:U2\|cc\[4\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { vga_16:U2|cc[4] } "NODE_NAME" } } { "vga_16.vhd" "" { Text "D:/altera/quartus60/program/ps2/vga_16.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.623 ns) + CELL(0.442 ns) 2.065 ns vga_16:U2\|Equal1~25 2 COMB LC_X21_Y13_N0 4 " "Info: 2: + IC(1.623 ns) + CELL(0.442 ns) = 2.065 ns; Loc. = LC_X21_Y13_N0; Fanout = 4; COMB Node = 'vga_16:U2\|Equal1~25'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.065 ns" { vga_16:U2|cc[4] vga_16:U2|Equal1~25 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1837 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.555 ns) + CELL(0.478 ns) 4.098 ns vga_16:U2\|cc\[2\] 3 REG LC_X15_Y13_N6 21 " "Info: 3: + IC(1.555 ns) + CELL(0.478 ns) = 4.098 ns; Loc. = LC_X15_Y13_N6; Fanout = 21; REG Node = 'vga_16:U2\|cc\[2\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.033 ns" { vga_16:U2|Equal1~25 vga_16:U2|cc[2] } "NODE_NAME" } } { "vga_16.vhd" "" { Text "D:/altera/quartus60/program/ps2/vga_16.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.920 ns ( 22.45 % ) " "Info: Total cell delay = 0.920 ns ( 22.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.178 ns ( 77.55 % ) " "Info: Total interconnect delay = 3.178 ns ( 77.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.098 ns" { vga_16:U2|cc[4] vga_16:U2|Equal1~25 vga_16:U2|cc[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.098 ns" { vga_16:U2|cc[4] vga_16:U2|Equal1~25 vga_16:U2|cc[2] } { 0.000ns 1.623ns 1.555ns } { 0.000ns 0.442ns 0.478ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLKIN destination 8.234 ns + Shortest register " "Info: + Shortest clock path from clock \"CLKIN\" to destination register is 8.234 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLKIN 1 CLK PIN_153 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 7; CLK Node = 'CLKIN'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLKIN } "NODE_NAME" } } { "ps2.vhd" "" { Text "D:/altera/quartus60/program/ps2/ps2.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.990 ns) + CELL(0.935 ns) 3.394 ns vga_16:U2\|fs\[5\] 2 REG LC_X7_Y12_N7 7 " "Info: 2: + IC(0.990 ns) + CELL(0.935 ns) = 3.394 ns; Loc. = LC_X7_Y12_N7; Fanout = 7; REG Node = 'vga_16:U2\|fs\[5\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.925 ns" { CLKIN vga_16:U2|fs[5] } "NODE_NAME" } } { "vga_16.vhd" "" { Text "D:/altera/quartus60/program/ps2/vga_16.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.129 ns) + CELL(0.711 ns) 8.234 ns vga_16:U2\|cc\[2\] 3 REG LC_X15_Y13_N6 21 " "Info: 3: + IC(4.129 ns) + CELL(0.711 ns) = 8.234 ns; Loc. = LC_X15_Y13_N6; Fanout = 21; REG Node = 'vga_16:U2\|cc\[2\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.840 ns" { vga_16:U2|fs[5] vga_16:U2|cc[2] } "NODE_NAME" } } { "vga_16.vhd" "" { Text "D:/altera/quartus60/program/ps2/vga_16.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 37.83 % ) " "Info: Total cell delay = 3.115 ns ( 37.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.119 ns ( 62.17 % ) " "Info: Total interconnect delay = 5.119 ns ( 62.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.234 ns" { CLKIN vga_16:U2|fs[5] vga_16:U2|cc[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "8.234 ns" { CLKIN CLKIN~out0 vga_16:U2|fs[5] vga_16:U2|cc[2] } { 0.000ns 0.000ns 0.990ns 4.129ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLKIN source 8.234 ns - Longest register " "Info: - Longest clock path from clock \"CLKIN\" to source register is 8.234 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLKIN 1 CLK PIN_153 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 7; CLK Node = 'CLKIN'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLKIN } "NODE_NAME" } } { "ps2.vhd" "" { Text "D:/altera/quartus60/program/ps2/ps2.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.990 ns) + CELL(0.935 ns) 3.394 ns vga_16:U2\|fs\[5\] 2 REG LC_X7_Y12_N7 7 " "Info: 2: + IC(0.990 ns) + CELL(0.935 ns) = 3.394 ns; Loc. = LC_X7_Y12_N7; Fanout = 7; REG Node = 'vga_16:U2\|fs\[5\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.925 ns" { CLKIN vga_16:U2|fs[5] } "NODE_NAME" } } { "vga_16.vhd" "" { Text "D:/altera/quartus60/program/ps2/vga_16.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.129 ns) + CELL(0.711 ns) 8.234 ns vga_16:U2\|cc\[4\] 3 REG LC_X15_Y13_N7 20 " "Info: 3: + IC(4.129 ns) + CELL(0.711 ns) = 8.234 ns; Loc. = LC_X15_Y13_N7; Fanout = 20; REG Node = 'vga_16:U2\|cc\[4\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.840 ns" { vga_16:U2|fs[5] vga_16:U2|cc[4] } "NODE_NAME" } } { "vga_16.vhd" "" { Text "D:/altera/quartus60/program/ps2/vga_16.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 37.83 % ) " "Info: Total cell delay = 3.115 ns ( 37.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.119 ns ( 62.17 % ) " "Info: Total interconnect delay = 5.119 ns ( 62.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.234 ns" { CLKIN vga_16:U2|fs[5] vga_16:U2|cc[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "8.234 ns" { CLKIN CLKIN~out0 vga_16:U2|fs[5] vga_16:U2|cc[4] } { 0.000ns 0.000ns 0.990ns 4.129ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.234 ns" { CLKIN vga_16:U2|fs[5] vga_16:U2|cc[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "8.234 ns" { CLKIN CLKIN~out0 vga_16:U2|fs[5] vga_16:U2|cc[2] } { 0.000ns 0.000ns 0.990ns 4.129ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.234 ns" { CLKIN vga_16:U2|fs[5] vga_16:U2|cc[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "8.234 ns" { CLKIN CLKIN~out0 vga_16:U2|fs[5] vga_16:U2|cc[4] } { 0.000ns 0.000ns 0.990ns 4.129ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "vga_16.vhd" "" { Text "D:/altera/quartus60/program/ps2/vga_16.vhd" 54 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "vga_16.vhd" "" { Text "D:/altera/quartus60/program/ps2/vga_16.vhd" 54 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.098 ns" { vga_16:U2|cc[4] vga_16:U2|Equal1~25 vga_16:U2|cc[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.098 ns" { vga_16:U2|cc[4] vga_16:U2|Equal1~25 vga_16:U2|cc[2] } { 0.000ns 1.623ns 1.555ns } { 0.000ns 0.442ns 0.478ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.234 ns" { CLKIN vga_16:U2|fs[5] vga_16:U2|cc[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "8.234 ns" { CLKIN CLKIN~out0 vga_16:U2|fs[5] vga_16:U2|cc[2] } { 0.000ns 0.000ns 0.990ns 4.129ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.234 ns" { CLKIN vga_16:U2|fs[5] vga_16:U2|cc[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "8.234 ns" { CLKIN CLKIN~out0 vga_16:U2|fs[5] vga_16:U2|cc[4] } { 0.000ns 0.000ns 0.990ns 4.129ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "CLK KBCLK CLKIN 5.579 ns register " "Info: tsu for register \"CLK\" (data pin = \"KBCLK\", clock pin = \"CLKIN\") is 5.579 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.753 ns + Longest pin register " "Info: + Longest pin to register delay is 8.753 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns KBCLK 1 PIN PIN_240 1 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_240; Fanout = 1; PIN Node = 'KBCLK'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { KBCLK } "NODE_NAME" } } { "ps2.vhd" "" { Text "D:/altera/quartus60/program/ps2/ps2.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.969 ns) + CELL(0.309 ns) 8.753 ns CLK 2 REG LC_X8_Y13_N2 28 " "Info: 2: + IC(6.969 ns) + CELL(0.309 ns) = 8.753 ns; Loc. = LC_X8_Y13_N2; Fanout = 28; REG Node = 'CLK'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.278 ns" { KBCLK CLK } "NODE_NAME" } } { "ps2.vhd" "" { Text "D:/altera/quartus60/program/ps2/ps2.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.784 ns ( 20.38 % ) " "Info: Total cell delay = 1.784 ns ( 20.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.969 ns ( 79.62 % ) " "Info: Total interconnect delay = 6.969 ns ( 79.62 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.753 ns" { KBCLK CLK } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "8.753 ns" { KBCLK KBCLK~out0 CLK } { 0.000ns 0.000ns 6.969ns } { 0.000ns 1.475ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "ps2.vhd" "" { Text "D:/altera/quartus60/program/ps2/ps2.vhd" 36 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLKIN destination 3.211 ns - Shortest register " "Info: - Shortest clock path from clock \"CLKIN\" to destination register is 3.211 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLKIN 1 CLK PIN_153 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 7; CLK Node = 'CLKIN'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLKIN } "NODE_NAME" } } { "ps2.vhd" "" { Text "D:/altera/quartus60/program/ps2/ps2.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.711 ns) 3.211 ns CLK 2 REG LC_X8_Y13_N2 28 " "Info: 2: + IC(1.031 ns) + CELL(0.711 ns) = 3.211 ns; Loc. = LC_X8_Y13_N2; Fanout = 28; REG Node = 'CLK'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.742 ns" { CLKIN CLK } "NODE_NAME" } } { "ps2.vhd" "" { Text "D:/altera/quartus60/program/ps2/ps2.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 67.89 % ) " "Info: Total cell delay = 2.180 ns ( 67.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.031 ns ( 32.11 % ) " "Info: Total interconnect delay = 1.031 ns ( 32.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.211 ns" { CLKIN CLK } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.211 ns" { CLKIN CLKIN~out0 CLK } { 0.000ns 0.000ns 1.031ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.753 ns" { KBCLK CLK } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "8.753 ns" { KBCLK KBCLK~out0 CLK } { 0.000ns 0.000ns 6.969ns } { 0.000ns 1.475ns 0.309ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.211 ns" { CLKIN CLK } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.211 ns" { CLKIN CLKIN~out0 CLK } { 0.000ns 0.000ns 1.031ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLKIN r vga_16:U2\|ll\[0\] 33.206 ns register " "Info: tco from clock \"CLKIN\" to destination pin \"r\" through register \"vga_16:U2\|ll\[0\]\" is 33.206 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLKIN source 13.511 ns + Longest register " "Info: + Longest clock path from clock \"CLKIN\" to source register is 13.511 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLKIN 1 CLK PIN_153 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 7; CLK Node = 'CLKIN'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLKIN } "NODE_NAME" } } { "ps2.vhd" "" { Text "D:/altera/quartus60/program/ps2/ps2.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.990 ns) + CELL(0.935 ns) 3.394 ns vga_16:U2\|fs\[5\] 2 REG LC_X7_Y12_N7 7 " "Info: 2: + IC(0.990 ns) + CELL(0.935 ns) = 3.394 ns; Loc. = LC_X7_Y12_N7; Fanout = 7; REG Node = 'vga_16:U2\|fs\[5\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.925 ns" { CLKIN vga_16:U2|fs[5] } "NODE_NAME" } } { "vga_16.vhd" "" { Text "D:/altera/quartus60/program/ps2/vga_16.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.129 ns) + CELL(0.935 ns) 8.458 ns vga_16:U2\|cc\[4\] 3 REG LC_X15_Y13_N7 20 " "Info: 3: + IC(4.129 ns) + CELL(0.935 ns) = 8.458 ns; Loc. = LC_X15_Y13_N7; Fanout = 20; REG Node = 'vga_16:U2\|cc\[4\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.064 ns" { vga_16:U2|fs[5] vga_16:U2|cc[4] } "NODE_NAME" } } { "vga_16.vhd" "" { Text "D:/altera/quartus60/program/ps2/vga_16.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.342 ns) + CELL(0.711 ns) 13.511 ns vga_16:U2\|ll\[0\] 4 REG LC_X23_Y15_N6 7 " "Info: 4: + IC(4.342 ns) + CELL(0.711 ns) = 13.511 ns; Loc. = LC_X23_Y15_N6; Fanout = 7; REG Node = 'vga_16:U2\|ll\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.053 ns" { vga_16:U2|cc[4] vga_16:U2|ll[0] } "NODE_NAME" } } { "vga_16.vhd" "" { Text "D:/altera/quartus60/program/ps2/vga_16.vhd" 64 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.050 ns ( 29.98 % ) " "Info: Total cell delay = 4.050 ns ( 29.98 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.461 ns ( 70.02 % ) " "Info: Total interconnect delay = 9.461 ns ( 70.02 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "13.511 ns" { CLKIN vga_16:U2|fs[5] vga_16:U2|cc[4] vga_16:U2|ll[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "13.511 ns" { CLKIN CLKIN~out0 vga_16:U2|fs[5] vga_16:U2|cc[4] vga_16:U2|ll[0] } { 0.000ns 0.000ns 0.990ns 4.129ns 4.342ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "vga_16.vhd" "" { Text "D:/altera/quartus60/program/ps2/vga_16.vhd" 64 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "19.471 ns + Longest register pin " "Info: + Longest register to pin delay is 19.471 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vga_16:U2\|ll\[0\] 1 REG LC_X23_Y15_N6 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X23_Y15_N6; Fanout = 7; REG Node = 'vga_16:U2\|ll\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { vga_16:U2|ll[0] } "NODE_NAME" } } { "vga_16.vhd" "" { Text "D:/altera/quartus60/program/ps2/vga_16.vhd" 64 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.204 ns) + CELL(0.590 ns) 1.794 ns vga_16:U2\|LessThan30~131 2 COMB LC_X23_Y15_N7 4 " "Info: 2: + IC(1.204 ns) + CELL(0.590 ns) = 1.794 ns; Loc. = LC_X23_Y15_N7; Fanout = 4; COMB Node = 'vga_16:U2\|LessThan30~131'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.794 ns" { vga_16:U2|ll[0] vga_16:U2|LessThan30~131 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1657 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.780 ns) + CELL(0.114 ns) 2.688 ns vga_16:U2\|LessThan30~132 3 COMB LC_X24_Y15_N8 3 " "Info: 3: + IC(0.780 ns) + CELL(0.114 ns) = 2.688 ns; Loc. = LC_X24_Y15_N8; Fanout = 3; COMB Node = 'vga_16:U2\|LessThan30~132'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.894 ns" { vga_16:U2|LessThan30~131 vga_16:U2|LessThan30~132 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1657 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.597 ns) + CELL(0.590 ns) 4.875 ns vga_16:U2\|process4~1641 4 COMB LC_X23_Y14_N1 1 " "Info: 4: + IC(1.597 ns) + CELL(0.590 ns) = 4.875 ns; Loc. = LC_X23_Y14_N1; Fanout = 1; COMB Node = 'vga_16:U2\|process4~1641'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.187 ns" { vga_16:U2|LessThan30~132 vga_16:U2|process4~1641 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.441 ns) + CELL(0.590 ns) 5.906 ns vga_16:U2\|process4~1642 5 COMB LC_X23_Y14_N2 6 " "Info: 5: + IC(0.441 ns) + CELL(0.590 ns) = 5.906 ns; Loc. = LC_X23_Y14_N2; Fanout = 6; COMB Node = 'vga_16:U2\|process4~1642'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.031 ns" { vga_16:U2|process4~1641 vga_16:U2|process4~1642 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.656 ns) + CELL(0.590 ns) 8.152 ns vga_16:U2\|rgbp\[2\]~4149 6 COMB LC_X21_Y13_N6 1 " "Info: 6: + IC(1.656 ns) + CELL(0.590 ns) = 8.152 ns; Loc. = LC_X21_Y13_N6; Fanout = 1; COMB Node = 'vga_16:U2\|rgbp\[2\]~4149'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.246 ns" { vga_16:U2|process4~1642 vga_16:U2|rgbp[2]~4149 } "NODE_NAME" } } { "vga_16.vhd" "" { Text "D:/altera/quartus60/program/ps2/vga_16.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.425 ns) + CELL(0.590 ns) 9.167 ns vga_16:U2\|rgbp\[2\]~4152 7 COMB LC_X21_Y13_N2 1 " "Info: 7: + IC(0.425 ns) + CELL(0.590 ns) = 9.167 ns; Loc. = LC_X21_Y13_N2; Fanout = 1; COMB Node = 'vga_16:U2\|rgbp\[2\]~4152'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.015 ns" { vga_16:U2|rgbp[2]~4149 vga_16:U2|rgbp[2]~4152 } "NODE_NAME" } } { "vga_16.vhd" "" { Text "D:/altera/quartus60/program/ps2/vga_16.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.924 ns) + CELL(0.590 ns) 11.681 ns vga_16:U2\|rgbp\[2\]~4160 8 COMB LC_X23_Y15_N2 1 " "Info: 8: + IC(1.924 ns) + CELL(0.590 ns) = 11.681 ns; Loc. = LC_X23_Y15_N2; Fanout = 1; COMB Node = 'vga_16:U2\|rgbp\[2\]~4160'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.514 ns" { vga_16:U2|rgbp[2]~4152 vga_16:U2|rgbp[2]~4160 } "NODE_NAME" } } { "vga_16.vhd" "" { Text "D:/altera/quartus60/program/ps2/vga_16.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.423 ns) + CELL(0.590 ns) 12.694 ns vga_16:U2\|r 9 COMB LC_X23_Y15_N9 1 " "Info: 9: + IC(0.423 ns) + CELL(0.590 ns) = 12.694 ns; Loc. = LC_X23_Y15_N9; Fanout = 1; COMB Node = 'vga_16:U2\|r'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.013 ns" { vga_16:U2|rgbp[2]~4160 vga_16:U2|r } "NODE_NAME" } } { "vga_16.vhd" "" { Text "D:/altera/quartus60/program/ps2/vga_16.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.653 ns) + CELL(2.124 ns) 19.471 ns r 10 PIN PIN_160 0 " "Info: 10: + IC(4.653 ns) + CELL(2.124 ns) = 19.471 ns; Loc. = PIN_160; Fanout = 0; PIN Node = 'r'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.777 ns" { vga_16:U2|r r } "NODE_NAME" } } { "ps2.vhd" "" { Text "D:/altera/quartus60/program/ps2/ps2.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.368 ns ( 32.71 % ) " "Info: Total cell delay = 6.368 ns ( 32.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "13.103 ns ( 67.29 % ) " "Info: Total interconnect delay = 13.103 ns ( 67.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "19.471 ns" { vga_16:U2|ll[0] vga_16:U2|LessThan30~131 vga_16:U2|LessThan30~132 vga_16:U2|process4~1641 vga_16:U2|process4~1642 vga_16:U2|rgbp[2]~4149 vga_16:U2|rgbp[2]~4152 vga_16:U2|rgbp[2]~4160 vga_16:U2|r r } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "19.471 ns" { vga_16:U2|ll[0] vga_16:U2|LessThan30~131 vga_16:U2|LessThan30~132 vga_16:U2|process4~1641 vga_16:U2|process4~1642 vga_16:U2|rgbp[2]~4149 vga_16:U2|rgbp[2]~4152 vga_16:U2|rgbp[2]~4160 vga_16:U2|r r } { 0.000ns 1.204ns 0.780ns 1.597ns 0.441ns 1.656ns 0.425ns 1.924ns 0.423ns 4.653ns } { 0.000ns 0.590ns 0.114ns 0.590ns 0.590ns 0.590ns 0.590ns 0.590ns 0.590ns 2.124ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "13.511 ns" { CLKIN vga_16:U2|fs[5] vga_16:U2|cc[4] vga_16:U2|ll[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "13.511 ns" { CLKIN CLKIN~out0 vga_16:U2|fs[5] vga_16:U2|cc[4] vga_16:U2|ll[0] } { 0.000ns 0.000ns 0.990ns 4.129ns 4.342ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "19.471 ns" { vga_16:U2|ll[0] vga_16:U2|LessThan30~131 vga_16:U2|LessThan30~132 vga_16:U2|process4~1641 vga_16:U2|process4~1642 vga_16:U2|rgbp[2]~4149 vga_16:U2|rgbp[2]~4152 vga_16:U2|rgbp[2]~4160 vga_16:U2|r r } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "19.471 ns" { vga_16:U2|ll[0] vga_16:U2|LessThan30~131 vga_16:U2|LessThan30~132 vga_16:U2|process4~1641 vga_16:U2|process4~1642 vga_16:U2|rgbp[2]~4149 vga_16:U2|rgbp[2]~4152 vga_16:U2|rgbp[2]~4160 vga_16:U2|r r } { 0.000ns 1.204ns 0.780ns 1.597ns 0.441ns 1.656ns 0.425ns 1.924ns 0.423ns 4.653ns } { 0.000ns 0.590ns 0.114ns 0.590ns 0.590ns 0.590ns 0.590ns 0.590ns 0.590ns 2.124ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}