count_top.hier_info

用键盘控制FPGA

|count_top
rst => counter:U1.RESET
clkin => vga_16:U3.clk
clkin => N[0].CLK
clkin => N[1].CLK
clkin => N[2].CLK
clkin => N[3].CLK
clkin => N[4].CLK
clkin => N[5].CLK
clkin => N[6].CLK
clkin => N[7].CLK
clkin => N[8].CLK
clkin => N[9].CLK
clkin => N[10].CLK
clkin => N[11].CLK
clkin => N[12].CLK
clkin => N[13].CLK
clkin => N[14].CLK
clkin => N[15].CLK
clkin => N[16].CLK
clkin => N[17].CLK
clkin => N[18].CLK
clkin => N[19].CLK
clkin => N[20].CLK
clkin => N[21].CLK
clkin => N[22].CLK
clkin => N[23].CLK
ld => counter:U1.LOAD
up => counter:U1.DIR
hs <= vga_16:U3.hs
vs <= vga_16:U3.vs
r[0] <= vga_16:U3.r
r[1] <= vga_16:U3.r
r[2] <= vga_16:U3.r
g[0] <= vga_16:U3.g
g[1] <= vga_16:U3.g
g[2] <= vga_16:U3.g
b[0] <= vga_16:U3.b
b[1] <= vga_16:U3.b


|count_top|counter:U1
CLK => COUNT[0]~reg0.CLK
CLK => COUNT[1]~reg0.CLK
CLK => COUNT[2]~reg0.CLK
CLK => COUNT[3]~reg0.CLK
CLK => COUNT[4]~reg0.CLK
CLK => COUNT[5]~reg0.CLK
CLK => COUNT[6]~reg0.CLK
CLK => COUNT[7]~reg0.CLK
CLK => COUNT[8]~reg0.CLK
CLK => COUNT[9]~reg0.CLK
CLK => COUNT[10]~reg0.CLK
CLK => COUNT[11]~reg0.CLK
CLK => COUNT[12]~reg0.CLK
CLK => COUNT[13]~reg0.CLK
CLK => COUNT[14]~reg0.CLK
CLK => COUNT[15]~reg0.CLK
RESET => COUNT[0]~reg0.ACLR
RESET => COUNT[1]~reg0.ACLR
RESET => COUNT[2]~reg0.ACLR
RESET => COUNT[3]~reg0.ACLR
RESET => COUNT[4]~reg0.ACLR
RESET => COUNT[5]~reg0.ACLR
RESET => COUNT[6]~reg0.ACLR
RESET => COUNT[7]~reg0.ACLR
RESET => COUNT[8]~reg0.ACLR
RESET => COUNT[9]~reg0.ACLR
RESET => COUNT[10]~reg0.ACLR
RESET => COUNT[11]~reg0.ACLR
RESET => COUNT[12]~reg0.ACLR
RESET => COUNT[13]~reg0.ACLR
RESET => COUNT[14]~reg0.ACLR
RESET => COUNT[15]~reg0.ACLR
CE => COUNT~48.OUTPUTSELECT
CE => COUNT~49.OUTPUTSELECT
CE => COUNT~50.OUTPUTSELECT
CE => COUNT~51.OUTPUTSELECT
CE => COUNT~52.OUTPUTSELECT
CE => COUNT~53.OUTPUTSELECT
CE => COUNT~54.OUTPUTSELECT
CE => COUNT~55.OUTPUTSELECT
CE => COUNT~56.OUTPUTSELECT
CE => COUNT~57.OUTPUTSELECT
CE => COUNT~58.OUTPUTSELECT
CE => COUNT~59.OUTPUTSELECT
CE => COUNT~60.OUTPUTSELECT
CE => COUNT~61.OUTPUTSELECT
CE => COUNT~62.OUTPUTSELECT
CE => COUNT~63.OUTPUTSELECT
LOAD => COUNT~32.OUTPUTSELECT
LOAD => COUNT~33.OUTPUTSELECT
LOAD => COUNT~34.OUTPUTSELECT
LOAD => COUNT~35.OUTPUTSELECT
LOAD => COUNT~36.OUTPUTSELECT
LOAD => COUNT~37.OUTPUTSELECT
LOAD => COUNT~38.OUTPUTSELECT
LOAD => COUNT~39.OUTPUTSELECT
LOAD => COUNT~40.OUTPUTSELECT
LOAD => COUNT~41.OUTPUTSELECT
LOAD => COUNT~42.OUTPUTSELECT
LOAD => COUNT~43.OUTPUTSELECT
LOAD => COUNT~44.OUTPUTSELECT
LOAD => COUNT~45.OUTPUTSELECT
LOAD => COUNT~46.OUTPUTSELECT
LOAD => COUNT~47.OUTPUTSELECT
DIR => COUNT~16.OUTPUTSELECT
DIR => COUNT~17.OUTPUTSELECT
DIR => COUNT~18.OUTPUTSELECT
DIR => COUNT~19.OUTPUTSELECT
DIR => COUNT~20.OUTPUTSELECT
DIR => COUNT~21.OUTPUTSELECT
DIR => COUNT~22.OUTPUTSELECT
DIR => COUNT~23.OUTPUTSELECT
DIR => COUNT~24.OUTPUTSELECT
DIR => COUNT~25.OUTPUTSELECT
DIR => COUNT~26.OUTPUTSELECT
DIR => COUNT~27.OUTPUTSELECT
DIR => COUNT~28.OUTPUTSELECT
DIR => COUNT~29.OUTPUTSELECT
DIR => COUNT~30.OUTPUTSELECT
DIR => COUNT~31.OUTPUTSELECT
DIN[0] => COUNT~47.DATAB
DIN[1] => COUNT~46.DATAB
DIN[2] => COUNT~45.DATAB
DIN[3] => COUNT~44.DATAB
DIN[4] => COUNT~43.DATAB
DIN[5] => COUNT~42.DATAB
DIN[6] => COUNT~41.DATAB
DIN[7] => COUNT~40.DATAB
DIN[8] => COUNT~39.DATAB
DIN[9] => COUNT~38.DATAB
DIN[10] => COUNT~37.DATAB
DIN[11] => COUNT~36.DATAB
DIN[12] => COUNT~35.DATAB
DIN[13] => COUNT~34.DATAB
DIN[14] => COUNT~33.DATAB
DIN[15] => COUNT~32.DATAB
COUNT[0] <= COUNT[0]~reg0
COUNT[1] <= COUNT[1]~reg0
COUNT[2] <= COUNT[2]~reg0
COUNT[3] <= COUNT[3]~reg0
COUNT[4] <= COUNT[4]~reg0
COUNT[5] <= COUNT[5]~reg0
COUNT[6] <= COUNT[6]~reg0
COUNT[7] <= COUNT[7]~reg0
COUNT[8] <= COUNT[8]~reg0
COUNT[9] <= COUNT[9]~reg0
COUNT[10] <= COUNT[10]~reg0
COUNT[11] <= COUNT[11]~reg0
COUNT[12] <= COUNT[12]~reg0
COUNT[13] <= COUNT[13]~reg0
COUNT[14] <= COUNT[14]~reg0
COUNT[15] <= COUNT[15]~reg0


|count_top|HEX2LED_4:U2
HEX[0] => Mux0.IN19
HEX[0] => Mux1.IN19
HEX[0] => Mux2.IN19
HEX[0] => Mux3.IN19
HEX[0] => Mux4.IN19
HEX[0] => Mux5.IN19
HEX[0] => Mux6.IN19
HEX[1] => Mux0.IN18
HEX[1] => Mux1.IN18
HEX[1] => Mux2.IN18
HEX[1] => Mux3.IN18
HEX[1] => Mux4.IN18
HEX[1] => Mux5.IN18
HEX[1] => Mux6.IN18
HEX[2] => Mux0.IN17
HEX[2] => Mux1.IN17
HEX[2] => Mux2.IN17
HEX[2] => Mux3.IN17
HEX[2] => Mux4.IN17
HEX[2] => Mux5.IN17
HEX[2] => Mux6.IN17
HEX[3] => Mux0.IN16
HEX[3] => Mux1.IN16
HEX[3] => Mux2.IN16
HEX[3] => Mux3.IN16
HEX[3] => Mux4.IN16
HEX[3] => Mux5.IN16
HEX[3] => Mux6.IN16
HEX[4] => Mux7.IN19
HEX[4] => Mux8.IN19
HEX[4] => Mux9.IN19
HEX[4] => Mux10.IN19
HEX[4] => Mux11.IN19
HEX[4] => Mux12.IN19
HEX[4] => Mux13.IN19
HEX[5] => Mux7.IN18
HEX[5] => Mux8.IN18
HEX[5] => Mux9.IN18
HEX[5] => Mux10.IN18
HEX[5] => Mux11.IN18
HEX[5] => Mux12.IN18
HEX[5] => Mux13.IN18
HEX[6] => Mux7.IN17
HEX[6] => Mux8.IN17
HEX[6] => Mux9.IN17
HEX[6] => Mux10.IN17
HEX[6] => Mux11.IN17
HEX[6] => Mux12.IN17
HEX[6] => Mux13.IN17
HEX[7] => Mux7.IN16
HEX[7] => Mux8.IN16
HEX[7] => Mux9.IN16
HEX[7] => Mux10.IN16
HEX[7] => Mux11.IN16
HEX[7] => Mux12.IN16
HEX[7] => Mux13.IN16
HEX[8] => Mux14.IN19
HEX[8] => Mux15.IN19
HEX[8] => Mux16.IN19
HEX[8] => Mux17.IN19
HEX[8] => Mux18.IN19
HEX[8] => Mux19.IN19
HEX[8] => Mux20.IN19
HEX[9] => Mux14.IN18
HEX[9] => Mux15.IN18
HEX[9] => Mux16.IN18
HEX[9] => Mux17.IN18
HEX[9] => Mux18.IN18
HEX[9] => Mux19.IN18
HEX[9] => Mux20.IN18
HEX[10] => Mux14.IN17
HEX[10] => Mux15.IN17
HEX[10] => Mux16.IN17
HEX[10] => Mux17.IN17
HEX[10] => Mux18.IN17
HEX[10] => Mux19.IN17
HEX[10] => Mux20.IN17
HEX[11] => Mux14.IN16
HEX[11] => Mux15.IN16
HEX[11] => Mux16.IN16
HEX[11] => Mux17.IN16
HEX[11] => Mux18.IN16
HEX[11] => Mux19.IN16
HEX[11] => Mux20.IN16
HEX[12] => Mux21.IN19
HEX[12] => Mux22.IN19
HEX[12] => Mux23.IN19
HEX[12] => Mux24.IN19
HEX[12] => Mux25.IN19
HEX[12] => Mux26.IN19
HEX[12] => Mux27.IN19
HEX[13] => Mux21.IN18
HEX[13] => Mux22.IN18
HEX[13] => Mux23.IN18
HEX[13] => Mux24.IN18
HEX[13] => Mux25.IN18
HEX[13] => Mux26.IN18
HEX[13] => Mux27.IN18
HEX[14] => Mux21.IN17
HEX[14] => Mux22.IN17
HEX[14] => Mux23.IN17
HEX[14] => Mux24.IN17
HEX[14] => Mux25.IN17
HEX[14] => Mux26.IN17
HEX[14] => Mux27.IN17
HEX[15] => Mux21.IN16
HEX[15] => Mux22.IN16
HEX[15] => Mux23.IN16
HEX[15] => Mux24.IN16
HEX[15] => Mux25.IN16
HEX[15] => Mux26.IN16
HEX[15] => Mux27.IN16
LED1[0] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE
LED1[1] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
LED1[2] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
LED1[3] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
LED1[4] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
LED1[5] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
LED1[6] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE
LED2[0] <= Mux13.DB_MAX_OUTPUT_PORT_TYPE
LED2[1] <= Mux12.DB_MAX_OUTPUT_PORT_TYPE
LED2[2] <= Mux11.DB_MAX_OUTPUT_PORT_TYPE
LED2[3] <= Mux10.DB_MAX_OUTPUT_PORT_TYPE
LED2[4] <= Mux9.DB_MAX_OUTPUT_PORT_TYPE
LED2[5] <= Mux8.DB_MAX_OUTPUT_PORT_TYPE
LED2[6] <= Mux7.DB_MAX_OUTPUT_PORT_TYPE
LED3[0] <= Mux20.DB_MAX_OUTPUT_PORT_TYPE
LED3[1] <= Mux19.DB_MAX_OUTPUT_PORT_TYPE
LED3[2] <= Mux18.DB_MAX_OUTPUT_PORT_TYPE
LED3[3] <= Mux17.DB_MAX_OUTPUT_PORT_TYPE
LED3[4] <= Mux16.DB_MAX_OUTPUT_PORT_TYPE
LED3[5] <= Mux15.DB_MAX_OUTPUT_PORT_TYPE
LED3[6] <= Mux14.DB_MAX_OUTPUT_PORT_TYPE
LED4[0] <= Mux27.DB_MAX_OUTPUT_PORT_TYPE
LED4[1] <= Mux26.DB_MAX_OUTPUT_PORT_TYPE
LED4[2] <= Mux25.DB_MAX_OUTPUT_PORT_TYPE
LED4[3] <= Mux24.DB_MAX_OUTPUT_PORT_TYPE
LED4[4] <= Mux23.DB_MAX_OUTPUT_PORT_TYPE
LED4[5] <= Mux22.DB_MAX_OUTPUT_PORT_TYPE
LED4[6] <= Mux21.DB_MAX_OUTPUT_PORT_TYPE


|count_top|vga_16:U3
clk => fs[0].CLK
clk => fs[1].CLK
clk => fs[2].CLK
clk => fs[3].CLK
clk => fs[4].CLK
clk => fs[5].CLK
hs <= LessThan0.DB_MAX_OUTPUT_PORT_TYPE
vs <= LessThan1.DB_MAX_OUTPUT_PORT_TYPE
r <= rgb~3.DB_MAX_OUTPUT_PORT_TYPE
g <= rgb~5.DB_MAX_OUTPUT_PORT_TYPE
b <= rgb~1.DB_MAX_OUTPUT_PORT_TYPE
innum[0] => process4~77.IN1
innum[1] => process4~76.IN1
innum[2] => process4~75.IN1
innum[3] => process4~74.IN1
innum[4] => process4~51.IN1
innum[5] => process4~50.IN1
innum[6] => process4~49.IN1
innum[7] => process4~48.IN1
innum[8] => process4~31.IN1
innum[9] => process4~30.IN1
innum[10] => process4~29.IN1
innum[11] => process4~28.IN1
innum[12] => process4~11.IN1
innum[13] => process4~10.IN1
innum[14] => process4~9.IN1
innum[15] => process4~8.IN1
innum0[0] => process4~86.IN1
innum0[1] => process4~84.IN1
innum0[2] => process4~82.IN1
innum0[3] => process4~80.IN1
innum0[4] => process4~59.IN1
innum0[5] => process4~57.IN1
innum0[6] => process4~55.IN1
innum0[7] => process4~53.IN1
innum0[8] => process4~39.IN1
innum0[9] => process4~37.IN1
innum0[10] => process4~35.IN1
innum0[11] => process4~33.IN1
innum0[12] => process4~19.IN1
innum0[13] => process4~17.IN1
innum0[14] => process4~15.IN1
innum0[15] => process4~13.IN1
innum1[0] => process4~62.IN1
innum1[1] => process4~69.IN1
innum1[2] => process4~72.IN1
innum1[3] => process4~66.IN1
innum1[4] => process4~71.IN1
innum1[5] => process4~68.IN1
innum1[6] => process4~64.IN1
innum2[0] => process4~41.IN1
innum2[1] => process4~45.IN1
innum2[2] => process4~47.IN1
innum2[3] => process4~43.IN1
innum2[4] => process4~46.IN1
innum2[5] => process4~44.IN1
innum2[6] => process4~42.IN1
innum3[0] => process4~21.IN1
innum3[1] => process4~25.IN1
innum3[2] => process4~27.IN1
innum3[3] => process4~23.IN1
innum3[4] => process4~26.IN1
innum3[5] => process4~24.IN1
innum3[6] => process4~22.IN1
innum4[0] => process4~1.IN1
innum4[1] => process4~5.IN1
innum4[2] => process4~7.IN1
innum4[3] => process4~3.IN1
innum4[4] => process4~6.IN1
innum4[5] => process4~4.IN1
innum4[6] => process4~2.IN1