ps2.tan.rpt

用键盘控制FPGA

+--------------------------------------------------------------------+
; th                                                                 ;
+---------------+-------------+-----------+--------+------+----------+
; Minimum Slack ; Required th ; Actual th ; From   ; To   ; To Clock ;
+---------------+-------------+-----------+--------+------+----------+
; N/A           ; None        ; -1.378 ns ; KBdata ; M[9] ; CLKIN    ;
; N/A           ; None        ; -5.527 ns ; KBCLK  ; CLK  ; CLKIN    ;
+---------------+-------------+-----------+--------+------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Fri Aug 17 17:56:54 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off ps2 -c ps2 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLKIN" is an undefined clock
Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "CLK" as buffer
    Info: Detected ripple clock "vga_16:U2|fs[5]" as buffer
    Info: Detected ripple clock "vga_16:U2|cc[4]" as buffer
Info: Clock "CLKIN" has Internal fmax of 229.41 MHz between source register "vga_16:U2|cc[4]" and destination register "vga_16:U2|cc[2]" (period= 4.359 ns)
    Info: + Longest register to register delay is 4.098 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X15_Y13_N7; Fanout = 20; REG Node = 'vga_16:U2|cc[4]'
        Info: 2: + IC(1.623 ns) + CELL(0.442 ns) = 2.065 ns; Loc. = LC_X21_Y13_N0; Fanout = 4; COMB Node = 'vga_16:U2|Equal1~25'
        Info: 3: + IC(1.555 ns) + CELL(0.478 ns) = 4.098 ns; Loc. = LC_X15_Y13_N6; Fanout = 21; REG Node = 'vga_16:U2|cc[2]'
        Info: Total cell delay = 0.920 ns ( 22.45 % )
        Info: Total interconnect delay = 3.178 ns ( 77.55 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "CLKIN" to destination register is 8.234 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 7; CLK Node = 'CLKIN'
            Info: 2: + IC(0.990 ns) + CELL(0.935 ns) = 3.394 ns; Loc. = LC_X7_Y12_N7; Fanout = 7; REG Node = 'vga_16:U2|fs[5]'
            Info: 3: + IC(4.129 ns) + CELL(0.711 ns) = 8.234 ns; Loc. = LC_X15_Y13_N6; Fanout = 21; REG Node = 'vga_16:U2|cc[2]'
            Info: Total cell delay = 3.115 ns ( 37.83 % )
            Info: Total interconnect delay = 5.119 ns ( 62.17 % )
        Info: - Longest clock path from clock "CLKIN" to source register is 8.234 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 7; CLK Node = 'CLKIN'
            Info: 2: + IC(0.990 ns) + CELL(0.935 ns) = 3.394 ns; Loc. = LC_X7_Y12_N7; Fanout = 7; REG Node = 'vga_16:U2|fs[5]'
            Info: 3: + IC(4.129 ns) + CELL(0.711 ns) = 8.234 ns; Loc. = LC_X15_Y13_N7; Fanout = 20; REG Node = 'vga_16:U2|cc[4]'
            Info: Total cell delay = 3.115 ns ( 37.83 % )
            Info: Total interconnect delay = 5.119 ns ( 62.17 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "CLK" (data pin = "KBCLK", clock pin = "CLKIN") is 5.579 ns
    Info: + Longest pin to register delay is 8.753 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_240; Fanout = 1; PIN Node = 'KBCLK'
        Info: 2: + IC(6.969 ns) + CELL(0.309 ns) = 8.753 ns; Loc. = LC_X8_Y13_N2; Fanout = 28; REG Node = 'CLK'
        Info: Total cell delay = 1.784 ns ( 20.38 % )
        Info: Total interconnect delay = 6.969 ns ( 79.62 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "CLKIN" to destination register is 3.211 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 7; CLK Node = 'CLKIN'
        Info: 2: + IC(1.031 ns) + CELL(0.711 ns) = 3.211 ns; Loc. = LC_X8_Y13_N2; Fanout = 28; REG Node = 'CLK'
        Info: Total cell delay = 2.180 ns ( 67.89 % )
        Info: Total interconnect delay = 1.031 ns ( 32.11 % )
Info: tco from clock "CLKIN" to destination pin "r" through register "vga_16:U2|ll[0]" is 33.206 ns
    Info: + Longest clock path from clock "CLKIN" to source register is 13.511 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 7; CLK Node = 'CLKIN'
        Info: 2: + IC(0.990 ns) + CELL(0.935 ns) = 3.394 ns; Loc. = LC_X7_Y12_N7; Fanout = 7; REG Node = 'vga_16:U2|fs[5]'
        Info: 3: + IC(4.129 ns) + CELL(0.935 ns) = 8.458 ns; Loc. = LC_X15_Y13_N7; Fanout = 20; REG Node = 'vga_16:U2|cc[4]'
        Info: 4: + IC(4.342 ns) + CELL(0.711 ns) = 13.511 ns; Loc. = LC_X23_Y15_N6; Fanout = 7; REG Node = 'vga_16:U2|ll[0]'
        Info: Total cell delay = 4.050 ns ( 29.98 % )
        Info: Total interconnect delay = 9.461 ns ( 70.02 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 19.471 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X23_Y15_N6; Fanout = 7; REG Node = 'vga_16:U2|ll[0]'
        Info: 2: + IC(1.204 ns) + CELL(0.590 ns) = 1.794 ns; Loc. = LC_X23_Y15_N7; Fanout = 4; COMB Node = 'vga_16:U2|LessThan30~131'
        Info: 3: + IC(0.780 ns) + CELL(0.114 ns) = 2.688 ns; Loc. = LC_X24_Y15_N8; Fanout = 3; COMB Node = 'vga_16:U2|LessThan30~132'
        Info: 4: + IC(1.597 ns) + CELL(0.590 ns) = 4.875 ns; Loc. = LC_X23_Y14_N1; Fanout = 1; COMB Node = 'vga_16:U2|process4~1641'
        Info: 5: + IC(0.441 ns) + CELL(0.590 ns) = 5.906 ns; Loc. = LC_X23_Y14_N2; Fanout = 6; COMB Node = 'vga_16:U2|process4~1642'
        Info: 6: + IC(1.656 ns) + CELL(0.590 ns) = 8.152 ns; Loc. = LC_X21_Y13_N6; Fanout = 1; COMB Node = 'vga_16:U2|rgbp[2]~4149'
        Info: 7: + IC(0.425 ns) + CELL(0.590 ns) = 9.167 ns; Loc. = LC_X21_Y13_N2; Fanout = 1; COMB Node = 'vga_16:U2|rgbp[2]~4152'
        Info: 8: + IC(1.924 ns) + CELL(0.590 ns) = 11.681 ns; Loc. = LC_X23_Y15_N2; Fanout = 1; COMB Node = 'vga_16:U2|rgbp[2]~4160'
        Info: 9: + IC(0.423 ns) + CELL(0.590 ns) = 12.694 ns; Loc. = LC_X23_Y15_N9; Fanout = 1; COMB Node = 'vga_16:U2|r'
        Info: 10: + IC(4.653 ns) + CELL(2.124 ns) = 19.471 ns; Loc. = PIN_160; Fanout = 0; PIN Node = 'r'
        Info: Total cell delay = 6.368 ns ( 32.71 % )
        Info: Total interconnect delay = 13.103 ns ( 67.29 % )
Info: th for register "M[9]