shake.v

来自「自己写的扩展功能时钟」· Verilog 代码 · 共 60 行

`timescale 1ns / 100ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    21:19:50 07/21/2007 
// Design Name: 
// Module Name:    shake 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module noshake(clk, b1, b2, b3, b4, noshakeb1, noshakeb2, noshakeb3, noshakeb4);
    input clk;
    input b1;
    input b2;
    input b3;
    input b4;
    output noshakeb1;
    output noshakeb2;
    output noshakeb3;
    output noshakeb4;
	 
	 parameter shaketime = 21'd1000000;
	 //parameter shaketime = 18'h0000f;
	 reg counten;
	 reg[20:0] shakecount;
	 reg sample;
	 reg noshakeb2,noshakeb3,noshakeb4;
	 
	 assign noshakeb1 = b1;	 
	 always @( posedge clk or negedge b1) begin
		if(b1 == 0)begin shakecount<=0; sample <=0; end
		else begin
			if(shakecount == shaketime)begin shakecount<=0; sample<=1; end
			else begin shakecount<=shakecount+1; sample<=0;end
		end
	 end
	 always @(posedge sample or negedge b1) begin
		 if(b1 == 0) begin
		 	{noshakeb2,noshakeb3,noshakeb4}<=3'b111;
		 end
		 else begin			 
			 if(b4 == 0){noshakeb2,noshakeb3,noshakeb4}<=3'b110;
			 else if(b3 == 0){noshakeb2,noshakeb3,noshakeb4}<=3'b101;
			 else if(b2 == 0){noshakeb2,noshakeb3,noshakeb4}<=3'b011;
			 else  {noshakeb2,noshakeb3,noshakeb4}<=3'b111;
		 end
		 
	 end
endmodule