task_example.v

该代码中有不少关于学习verilog HDL的例子,对初学者有帮助

module task_example(c,a,b);
output[7:0] c;
input[7:0] a,b;
reg[7:0] c;
task adder;
output[7:0] adder;
input[7:0] a,b;
reg c;
begin: adder_part
  integer i;
  c=0;
  for(i=0;i<=7;i=i+1)
    begin
      adder[i]=a[i]^b[i]^c;
      c=(a[i]^b[i])&c|a[i]&b[i];
    end
end
endtask
always@(a or b)
adder(c,a,b);
endmodule