smartsopc_board_cyclone_1c6.tan.rpt

来自「sopc开发板标准NIOSII模块」· RPT 代码 · 共 177 行 · 第 1/5 页

; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                                              ;
+---------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; Clock Node Name                             ; Clock Setting Name ; Type       ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset    ; Phase offset ;
+---------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; SYS_CLK:inst1|altpll:altpll_component|_clk0 ;                    ; PLL output ; 60.0 MHz         ; 0.000 ns      ; 0.000 ns     ; SYS_CLK1 ; 5                     ; 4                   ; -1.885 ns ;              ;
; SYS_CLK1                                    ;                    ; User Pin   ; 48.0 MHz         ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A       ;              ;
; altera_internal_jtag~TCKUTAP                ;                    ; User Pin   ; NONE             ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A       ;              ;
+---------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'SYS_CLK:inst1|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
+-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------+---------------------------------------------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                                                                                                               ; To                                                                                                                                                                               ; From Clock                                  ; To Clock                                    ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------+---------------------------------------------+-----------------------------+---------------------------+-------------------------+
; 0.700 ns                                ; 62.63 MHz ( period = 15.966 ns )                    ; SmartSOPC_Board_Cyclone_1C6:inst|cpu_0:the_cpu_0|i_read                                                                                                                            ; SmartSOPC_Board_Cyclone_1C6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[7]                                    ; SYS_CLK:inst1|altpll:altpll_component|_clk0 ; SYS_CLK:inst1|altpll:altpll_component|_clk0 ; 16.666 ns                   ; 15.633 ns                 ; 14.933 ns               ;
; 0.832 ns                                ; 63.16 MHz ( period = 15.834 ns )                    ; SmartSOPC_Board_Cyclone_1C6:inst|cpu_0:the_cpu_0|i_read                                                                                                                            ; SmartSOPC_Board_Cyclone_1C6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[5]                                    ; SYS_CLK:inst1|altpll:altpll_component|_clk0 ; SYS_CLK:inst1|altpll:altpll_component|_clk0 ; 16.666 ns                   ; 15.633 ns                 ; 14.801 ns               ;
; 0.990 ns                                ; 63.79 MHz ( period = 15.676 ns )                    ; SmartSOPC_Board_Cyclone_1C6:inst|cpu_0:the_cpu_0|M_alu_result[21]                                                                                                                  ; SmartSOPC_Board_Cyclone_1C6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[7]                                    ; SYS_CLK:inst1|altpll:altpll_component|_clk0 ; SYS_CLK:inst1|altpll:altpll_component|_clk0 ; 16.666 ns                   ; 15.633 ns                 ; 14.643 ns               ;
; 0.991 ns                                ; 63.80 MHz ( period = 15.675 ns )                    ; SmartSOPC_Board_Cyclone_1C6:inst|cpu_0:the_cpu_0|i_read                                                                                                                            ; SmartSOPC_Board_Cyclone_1C6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[6]                                    ; SYS_CLK:inst1|altpll:altpll_component|_clk0 ; SYS_CLK:inst1|altpll:altpll_component|_clk0 ; 16.666 ns                   ; 15.633 ns                 ; 14.642 ns               ;
; 1.122 ns                                ; 64.33 MHz ( period = 15.544 ns )                    ; SmartSOPC_Board_Cyclone_1C6:inst|cpu_0:the_cpu_0|M_alu_result[21]                                                                                                                  ; SmartSOPC_Board_Cyclone_1C6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[5]                                    ; SYS_CLK:inst1|altpll:altpll_component|_clk0 ; SYS_CLK:inst1|altpll:altpll_component|_clk0 ; 16.666 ns                   ; 15.633 ns                 ; 14.511 ns               ;
; 1.161 ns                                ; 64.50 MHz ( period = 15.505 ns )                    ; SmartSOPC_Board_Cyclone_1C6:inst|cpu_0:the_cpu_0|i_read                                                                                                                            ; SmartSOPC_Board_Cyclone_1C6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[9]                                    ; SYS_CLK:inst1|altpll:altpll_component|_clk0 ; SYS_CLK:inst1|altpll:altpll_component|_clk0 ; 16.666 ns                   ; 15.633 ns                 ; 14.472 ns               ;
; 1.175 ns                                ; 64.55 MHz ( period = 15.491 ns )                    ; SmartSOPC_Board_Cyclone_1C6:inst|cpu_0:the_cpu_0|i_read                                                                                                                            ; SmartSOPC_Board_Cyclone_1C6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[12]                                   ; SYS_CLK:inst1|altpll:altpll_component|_clk0 ; SYS_CLK:inst1|altpll:altpll_component|_clk0 ; 16.666 ns                   ; 15.633 ns                 ; 14.458 ns               ;
; 1.176 ns                                ; 64.56 MHz ( period = 15.490 ns )                    ; SmartSOPC_Board_Cyclone_1C6:inst|cpu_0:the_cpu_0|i_read                                                                                                                            ; SmartSOPC_Board_Cyclone_1C6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[20]                                   ; SYS_CLK:inst1|altpll:altpll_component|_clk0 ; SYS_CLK:inst1|altpll:altpll_component|_clk0 ; 16.666 ns                   ; 15.633 ns                 ; 14.457 ns               ;
; 1.183 ns                                ; 64.59 MHz ( period = 15.483 ns )                    ; SmartSOPC_Board_Cyclone_1C6:inst|cpu_0:the_cpu_0|i_read                                                                                                                            ; SmartSOPC_Board_Cyclone_1C6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[10]                                   ; SYS_CLK:inst1|altpll:altpll_component|_clk0 ; SYS_CLK:inst1|altpll:altpll_component|_clk0 ; 16.666 ns                   ; 15.633 ns                 ; 14.450 ns               ;