smartsopc_board_cyclone_1c6.tan.rpt

来自「sopc开发板标准NIOSII模块」· RPT 代码 · 共 177 行 · 第 1/5 页

programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
+------------------------------------------------------------+----------+----------------------------------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------+---------------------------------------------+--------------+
; Type                                                       ; Slack    ; Required Time                    ; Actual Time                      ; From                                                                                                                                      ; To                                                                                                                                                  ; From Clock                                  ; To Clock                                    ; Failed Paths ;
+------------------------------------------------------------+----------+----------------------------------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------+---------------------------------------------+--------------+
; Worst-case tsu                                             ; N/A      ; None                             ; 1.944 ns                         ; D[6]                                                                                                                                      ; SmartSOPC_Board_Cyclone_1C6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|incoming_tri_state_bridge_0_data[6] ;                                             ; SYS_CLK1                                    ; 0            ;
; Worst-case tco                                             ; N/A      ; None                             ; 2.671 ns                         ; SmartSOPC_Board_Cyclone_1C6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_writen ; nWE                                                                                                                                                 ; SYS_CLK1                                    ;                                             ; 0            ;
; Worst-case tpd                                             ; N/A      ; None                             ; 2.124 ns                         ; altera_internal_jtag~TDO                                                                                                                  ; altera_reserved_tdo                                                                                                                                 ;                                             ;                                             ; 0            ;
; Worst-case th                                              ; N/A      ; None                             ; 3.836 ns                         ; altera_internal_jtag~TMSUTAP                                                                                                              ; sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[10]                                                                            ;                                             ; altera_internal_jtag~TCKUTAP                ; 0            ;
; Clock Setup: 'SYS_CLK:inst1|altpll:altpll_component|_clk0' ; 0.700 ns ; 60.00 MHz ( period = 16.666 ns ) ; 62.63 MHz ( period = 15.966 ns ) ; SmartSOPC_Board_Cyclone_1C6:inst|cpu_0:the_cpu_0|i_read                                                                                   ; SmartSOPC_Board_Cyclone_1C6:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[7]       ; SYS_CLK:inst1|altpll:altpll_component|_clk0 ; SYS_CLK:inst1|altpll:altpll_component|_clk0 ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP'                ; N/A      ; None                             ; 89.59 MHz ( period = 11.162 ns ) ; sld_hub:sld_hub_inst|jtag_debug_mode_usr1                                                                                                 ; SmartSOPC_Board_Cyclone_1C6:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate                                ; altera_internal_jtag~TCKUTAP                ; altera_internal_jtag~TCKUTAP                ; 0            ;
; Clock Hold: 'SYS_CLK:inst1|altpll:altpll_component|_clk0'  ; 0.822 ns ; 60.00 MHz ( period = 16.666 ns ) ; N/A                              ; SmartSOPC_Board_Cyclone_1C6:inst|cpu_0:the_cpu_0|ic_fill_dp_offset[1]                                                                     ; SmartSOPC_Board_Cyclone_1C6:inst|cpu_0:the_cpu_0|ic_fill_dp_offset[1]                                                                               ; SYS_CLK:inst1|altpll:altpll_component|_clk0 ; SYS_CLK:inst1|altpll:altpll_component|_clk0 ; 0            ;
; Total number of failed paths                               ;          ;                                  ;                                  ;                                                                                                                                           ;                                                                                                                                                     ;                                             ;                                             ; 0            ;
+------------------------------------------------------------+----------+----------------------------------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------+---------------------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C6Q240C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;