balancedmult.vhd

FIR数字滤波器程序

);
U335 : MCELL21	PORT MAP(
	AIN => N24208, 
	AOUT => N24488, 
	BIN => N24948, 
	BOUT => N39228, 
	CIN => TEST106, 
	COUT => TEST107, 
	SUMIN => TEST95, 
	SUMOUT => Y9
);
U304 : MCELL21	PORT MAP(
	AIN => N28815, 
	AOUT => N10390, 
	BIN => N10077, 
	BOUT => N10128, 
	CIN => TEST36, 
	COUT => TEST38, 
	SUMIN => TEST16, 
	SUMOUT => TEST37
);
U336 : MCELL21	PORT MAP(
	AIN => N24488, 
	AOUT => N35137, 
	BIN => N24832, 
	BOUT => N39201, 
	CIN => TEST107, 
	COUT => TEST108, 
	SUMIN => TEST97, 
	SUMOUT => Y10
);
U305 : MCELL21	PORT MAP(
	AIN => N23192, 
	AOUT => N28815, 
	BIN => N22624, 
	BOUT => N23088, 
	CIN => TEST34, 
	COUT => TEST36, 
	SUMIN => TEST24, 
	SUMOUT => TEST35
);
U337 : MCELL21	PORT MAP(
	AIN => N35137, 
	AOUT => N25880, 
	BIN => N26288, 
	BOUT => N39174, 
	CIN => TEST108, 
	COUT => TEST109, 
	SUMIN => TEST99, 
	SUMOUT => Y11
);
U306 : MCELL21	PORT MAP(
	AIN => N23084, 
	AOUT => N23192, 
	BIN => N23152, 
	BOUT => N23164, 
	CIN => TEST32, 
	COUT => TEST34, 
	SUMIN => TEST22, 
	SUMOUT => TEST33
);
U338 : MCELL21	PORT MAP(
	AIN => N25880, 
	AOUT => N25744, 
	BIN => N26356, 
	BOUT => N39147, 
	CIN => TEST109, 
	COUT => TEST110, 
	SUMIN => TEST101, 
	SUMOUT => Y12
);
U307 : MCELL21	PORT MAP(
	AIN => N23336, 
	AOUT => N23084, 
	BIN => N23172, 
	BOUT => N22808, 
	CIN => TEST30, 
	COUT => TEST32, 
	SUMIN => TEST20, 
	SUMOUT => TEST31
);
U339 : MCELL21	PORT MAP(
	AIN => N25744, 
	AOUT => N26024, 
	BIN => N26484, 
	BOUT => N39120, 
	CIN => TEST110, 
	COUT => TEST111, 
	SUMIN => TEST103, 
	SUMOUT => Y13
);
U308 : MCELL21	PORT MAP(
	AIN => N23180, 
	AOUT => N22680, 
	BIN => N22808, 
	BOUT => N34737, 
	CIN => TEST45, 
	COUT => TEST47, 
	SUMIN => TEST33, 
	SUMOUT => TEST46
);
U309 : MCELL21	PORT MAP(
	AIN => N22680, 
	AOUT => N23264, 
	BIN => N23164, 
	BOUT => N34429, 
	CIN => TEST47, 
	COUT => TEST49, 
	SUMIN => TEST35, 
	SUMOUT => TEST48
);
U293 : MCELL11	PORT MAP(
	AIN => A0, 
	AOUT => N23188, 
	BIN => B1, 
	BOUT => N23512, 
	CIN => TEST1, 
	COUT => TEST3, 
	SUMIN => GND, 
	SUMOUT => TEST2
);
U294 : MCELL21	PORT MAP(
	AIN => N23188, 
	AOUT => N23076, 
	BIN => B2, 
	BOUT => N23100, 
	CIN => TEST3, 
	COUT => TEST5, 
	SUMIN => GND, 
	SUMOUT => TEST4
);
U295 : MCELL21	PORT MAP(
	AIN => N22860, 
	AOUT => N23092, 
	BIN => N23512, 
	BOUT => N23172, 
	CIN => TEST17, 
	COUT => TEST19, 
	SUMIN => TEST4, 
	SUMOUT => TEST18
);
U296 : MCELL21	PORT MAP(
	AIN => N23092, 
	AOUT => N22676, 
	BIN => N23100, 
	BOUT => N23152, 
	CIN => TEST19, 
	COUT => TEST21, 
	SUMIN => TEST6, 
	SUMOUT => TEST20
);
U297 : MCELL21	PORT MAP(
	AIN => N22676, 
	AOUT => N28640, 
	BIN => N23252, 
	BOUT => N22624, 
	CIN => TEST21, 
	COUT => TEST23, 
	SUMIN => TEST8, 
	SUMOUT => TEST22
);
U298 : MCELL21	PORT MAP(
	AIN => N28640, 
	AOUT => N10645, 
	BIN => N13556, 
	BOUT => N10077, 
	CIN => TEST23, 
	COUT => TEST0, 
	SUMIN => TEST10, 
	SUMOUT => TEST24
);
U299 : MCELL21	PORT MAP(
	AIN => N10645, 
	AOUT => N10543, 
	BIN => N11371, 
	BOUT => N09910, 
	CIN => TEST0, 
	COUT => TEST25, 
	SUMIN => TEST12, 
	SUMOUT => TEST16
);
U340 : MCELL21_1	PORT MAP(
	AIN => N10441, 
	AOUT => N38904, 
	BIN => N10963, 
	BOUT => N09687, 
	CIN => TEST27, 
	COUT => TEST29, 
	SUMIN => TEST15, 
	SUMOUT => TEST28
);
U310 : MCELL21	PORT MAP(
	AIN => N23264, 
	AOUT => N28980, 
	BIN => N23088, 
	BOUT => N33974, 
	CIN => TEST49, 
	COUT => TEST51, 
	SUMIN => TEST37, 
	SUMOUT => TEST50
);
U342 : MCELL21_1	PORT MAP(
	AIN => N08025, 
	AOUT => N38931, 
	BIN => N09687, 
	BOUT => N08427, 
	CIN => TEST42, 
	COUT => TEST44, 
	SUMIN => TEST29, 
	SUMOUT => TEST43
);
U343 : MCELL21_1	PORT MAP(
	AIN => N08762, 
	AOUT => N38958, 
	BIN => N08427, 
	BOUT => N34025, 
	CIN => TEST57, 
	COUT => TEST59, 
	SUMIN => TEST44, 
	SUMOUT => TEST58
);
U311 : MCELL21	PORT MAP(
	AIN => N28980, 
	AOUT => N10237, 
	BIN => N10128, 
	BOUT => N33923, 
	CIN => TEST51, 
	COUT => TEST53, 
	SUMIN => TEST39, 
	SUMOUT => TEST52
);
U312 : MCELL21	PORT MAP(
	AIN => N10237, 
	AOUT => N08683, 
	BIN => N08574, 
	BOUT => N33872, 
	CIN => TEST53, 
	COUT => TEST56, 
	SUMIN => TEST41, 
	SUMOUT => TEST54
);
U344 : MCELL21_1	PORT MAP(
	AIN => N25624, 
	AOUT => N38985, 
	BIN => N34025, 
	BOUT => N179382, 
	CIN => TEST72, 
	COUT => TEST74, 
	SUMIN => TEST59, 
	SUMOUT => TEST73
);
U345 : MCELL21_1	PORT MAP(
	AIN => N25700, 
	AOUT => N39012, 
	BIN => N179382, 
	BOUT => N25740, 
	CIN => TEST87, 
	COUT => TEST89, 
	SUMIN => TEST74, 
	SUMOUT => TEST88
);
U313 : MCELL21	PORT MAP(
	AIN => N08683, 
	AOUT => N08762, 
	BIN => N08348, 
	BOUT => N33821, 
	CIN => TEST56, 
	COUT => TEST57, 
	SUMIN => TEST43, 
	SUMOUT => TEST55
);
U314 : MCELL21	PORT MAP(
	AIN => N26020, 
	AOUT => N25624, 
	BIN => N33821, 
	BOUT => N25716, 
	CIN => TEST70, 
	COUT => TEST72, 
	SUMIN => TEST58, 
	SUMOUT => TEST71
);
U346 : MCELL21_1	PORT MAP(
	AIN => N25760, 
	AOUT => N39039, 
	BIN => N25740, 
	BOUT => N26368, 
	CIN => TEST102, 
	COUT => TEST104, 
	SUMIN => TEST89, 
	SUMOUT => TEST103
);
U347 : MCELL21_1	PORT MAP(
	AIN => N26024, 
	AOUT => N39066, 
	BIN => N26368, 
	BOUT => N39093, 
	CIN => TEST111, 
	COUT => Y15, 
	SUMIN => TEST104, 
	SUMOUT => Y14
);
U315 : MCELL21	PORT MAP(
	AIN => N25628, 
	AOUT => N26020, 
	BIN => N33872, 
	BOUT => N26348, 
	CIN => TEST68, 
	COUT => TEST70, 
	SUMIN => TEST55, 
	SUMOUT => TEST69
);
U316 : MCELLNONE	PORT MAP(
	AIN => A0, 
	AOUT => N23528, 
	BIN => B0, 
	BOUT => N23080, 
	CIN => GND, 
	COUT => TEST1, 
	SUMIN => GND, 
	SUMOUT => Y0
);
U348 : MCELL31	PORT MAP(
	AIN => N23076, 
	AOUT => N28498, 
	BIN => B3, 
	BOUT => N23252, 
	CIN => TEST5, 
	COUT => TEST7, 
	SUMIN => GND, 
	SUMOUT => TEST6
);
U317 : MCELL21	PORT MAP(
	AIN => N35622, 
	AOUT => N25628, 
	BIN => N33923, 
	BOUT => N26232, 
	CIN => TEST66, 
	COUT => TEST68, 
	SUMIN => TEST54, 
	SUMOUT => TEST67
);
U349 : MCELL41	PORT MAP(
	AIN => N28498, 
	AOUT => N11218, 
	BIN => B4, 
	BOUT => N13556, 
	CIN => TEST7, 
	COUT => TEST9, 
	SUMIN => GND, 
	SUMOUT => TEST8
);
U318 : MCELL21	PORT MAP(
	AIN => N24088, 
	AOUT => N35622, 
	BIN => N33974, 
	BOUT => N24836, 
	CIN => TEST64, 
	COUT => TEST66, 
	SUMIN => TEST52, 
	SUMOUT => TEST65
);
U319 : MCELL21	PORT MAP(
	AIN => N24484, 
	AOUT => N24088, 
	BIN => N34429, 
	BOUT => N24180, 
	CIN => TEST62, 
	COUT => TEST64, 
	SUMIN => TEST50, 
	SUMOUT => TEST63
);
U350 : MCELL51	PORT MAP(
	AIN => N11218, 
	AOUT => N11116, 
	BIN => B5, 
	BOUT => N11371, 
	CIN => TEST9, 
	COUT => TEST11, 
	SUMIN => GND, 
	SUMOUT => TEST10
);
U351 : MCELL61	PORT MAP(
	AIN => N11116, 
	AOUT => N11065, 
	BIN => B6, 
	BOUT => N11320, 
	CIN => TEST11, 
	COUT => TEST13, 
	SUMIN => GND, 
	SUMOUT => TEST12
);
U320 : MCELL21	PORT MAP(
	AIN => N24092, 
	AOUT => N24484, 
	BIN => N34737, 
	BOUT => N295285, 
	CIN => TEST60, 
	COUT => TEST62, 
	SUMIN => TEST48, 
	SUMOUT => TEST61
);
U352 : MCELL71	PORT MAP(
	AIN => N11065, 
	AOUT => N38601, 
	BIN => B7, 
	BOUT => N10963, 
	CIN => TEST13, 
	COUT => TEST15, 
	SUMIN => GND, 
	SUMOUT => TEST14
);
U353 : MCELL22	PORT MAP(
	AIN => A1, 
	AOUT => N22860, 
	BIN => B0, 
	BOUT => TEST117, 
	CIN => GND, 
	COUT => TEST17, 
	SUMIN => TEST2, 
	SUMOUT => Y1
);
U321 : MCELL21	PORT MAP(
	AIN => N24148, 
	AOUT => N24944, 
	BIN => N295285, 
	BOUT => N24468, 
	CIN => TEST75, 
	COUT => TEST77, 
	SUMIN => TEST63, 
	SUMOUT => TEST76
);
U322 : MCELL21	PORT MAP(
	AIN => N24944, 
	AOUT => N24164, 
	BIN => N24180, 
	BOUT => N24840, 
	CIN => TEST77, 
	COUT => TEST79, 
	SUMIN => TEST65, 
	SUMOUT => TEST78
);
U354 : MCELL24	PORT MAP(
	AIN => A2, 
	AOUT => N23336, 
	BIN => TEST117, 
	BOUT => TEST116, 
	CIN => GND, 
	COUT => TEST30, 
	SUMIN => TEST18, 
	SUMOUT => Y2
);
U355 : MCELL26	PORT MAP(
	AIN => A3, 
	AOUT => N23180, 
	BIN => TEST116, 
	BOUT => TEST115, 
	CIN => GND, 
	COUT => TEST45, 
	SUMIN => TEST31, 
	SUMOUT => Y3
);
U323 : MCELL21	PORT MAP(
	AIN => N24164, 
	AOUT => N35480, 
	BIN => N24836, 
	BOUT => N24204, 
	CIN => TEST79, 
	COUT => TEST81, 
	SUMIN => TEST67, 
	SUMOUT => TEST80
);
U356 : MCELL28	PORT MAP(
	AIN => A4, 
	AOUT => N24092, 
	BIN => TEST115, 
	BOUT => TEST114, 
	CIN => GND, 
	COUT => TEST60, 
	SUMIN => TEST46, 
	SUMOUT => Y4
);
U324 : MCELL21	PORT MAP(
	AIN => N35480, 
	AOUT => N25684, 
	BIN => N26232, 
	BOUT => N26364, 
	CIN => TEST81, 
	COUT => TEST83, 
	SUMIN => TEST69, 
	SUMOUT => TEST82
);
U325 : MCELL21	PORT MAP(
	AIN => N25684, 
	AOUT => N26480, 
	BIN => N26348, 
	BOUT => N26004, 
	CIN => TEST83, 
	COUT => TEST85, 
	SUMIN => TEST71, 
	SUMOUT => TEST84
);
U357 : MCELL210	PORT MAP(
	AIN => A5, 
	AOUT => N24148, 
	BIN => TEST114, 
	BOUT => TEST113, 
	CIN => GND, 
	COUT => TEST75, 
	SUMIN => TEST61, 
	SUMOUT => Y5
);
U358 : MCELL212	PORT MAP(
	AIN => A6, 
	AOUT => N24160, 
	BIN => TEST113, 
	BOUT => TEST112, 
	CIN => GND, 
	COUT => TEST90, 
	SUMIN => TEST76, 
	SUMOUT => Y6
);
U359 : MCELL214	PORT MAP(
	AIN => A7, 
	AOUT => N24344, 
	BIN => TEST112, 
	BOUT => N39282, 
	CIN => GND, 
	COUT => TEST105, 
	SUMIN => TEST91, 
	SUMOUT => Y7
);
U327 : MCELL21	PORT MAP(
	AIN => N26480, 
	AOUT => N25700, 
	BIN => N25716, 
	BOUT => N26376, 
	CIN => TEST85, 
	COUT => TEST87, 
	SUMIN => TEST73, 
	SUMOUT => TEST86
);
U328 : MCELL21	PORT MAP(
	AIN => N25680, 
	AOUT => N25760, 
	BIN => N26376, 
	BOUT => N26484, 
	CIN => TEST100, 
	COUT => TEST102, 
	SUMIN => TEST88, 
	SUMOUT => TEST101
);
U329 : MCELL21	PORT MAP(
	AIN => N25696, 
	AOUT => N25680, 
	BIN => N26004, 
	BOUT => N26356, 
	CIN => TEST98, 
	COUT => TEST100, 
	SUMIN => TEST86, 
	SUMOUT => TEST99
);
END STRUCTURE;