📄 balancedmult.vhd
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LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY BalancedMult IS PORT (
A0 : IN std_logic;
A1 : IN std_logic;
A2 : IN std_logic;
A3 : IN std_logic;
A4 : IN std_logic;
A5 : IN std_logic;
A6 : IN std_logic;
A7 : IN std_logic;
B0 : IN std_logic;
B1 : IN std_logic;
B2 : IN std_logic;
B3 : IN std_logic;
B4 : IN std_logic;
B5 : IN std_logic;
B6 : IN std_logic;
B7 : IN std_logic;
Y0 : OUT std_logic;
Y1 : OUT std_logic;
Y2 : OUT std_logic;
Y3 : OUT std_logic;
Y4 : OUT std_logic;
Y5 : OUT std_logic;
Y6 : OUT std_logic;
Y7 : OUT std_logic;
Y8 : OUT std_logic;
Y9 : OUT std_logic;
Y10 : OUT std_logic;
Y11 : OUT std_logic;
Y12 : OUT std_logic;
Y13 : OUT std_logic;
Y14 : OUT std_logic;
Y15 : OUT std_logic
);
END BalancedMult;
ARCHITECTURE STRUCTURE OF BalancedMult IS
-- COMPONENTS
COMPONENT MCELL21
PORT (
AIN : IN std_logic;
AOUT : OUT std_logic;
BIN : IN std_logic;
BOUT : OUT std_logic;
CIN : IN std_logic;
COUT : OUT std_logic;
SUMIN : IN std_logic;
SUMOUT : OUT std_logic
); END COMPONENT;
COMPONENT MCELL11
PORT (
AIN : IN std_logic;
AOUT : OUT std_logic;
BIN : IN std_logic;
BOUT : OUT std_logic;
CIN : IN std_logic;
COUT : OUT std_logic;
SUMIN : IN std_logic;
SUMOUT : OUT std_logic
); END COMPONENT;
COMPONENT MCELL21_1
PORT (
AIN : IN std_logic;
AOUT : OUT std_logic;
BIN : IN std_logic;
BOUT : OUT std_logic;
CIN : IN std_logic;
COUT : OUT std_logic;
SUMIN : IN std_logic;
SUMOUT : OUT std_logic
); END COMPONENT;
COMPONENT MCELLNONE
PORT (
AIN : IN std_logic;
AOUT : OUT std_logic;
BIN : IN std_logic;
BOUT : OUT std_logic;
CIN : IN std_logic;
COUT : OUT std_logic;
SUMIN : IN std_logic;
SUMOUT : OUT std_logic
); END COMPONENT;
COMPONENT MCELL31
PORT (
AIN : IN std_logic;
AOUT : OUT std_logic;
BIN : IN std_logic;
BOUT : OUT std_logic;
CIN : IN std_logic;
COUT : OUT std_logic;
SUMIN : IN std_logic;
SUMOUT : OUT std_logic
); END COMPONENT;
COMPONENT MCELL41
PORT (
AIN : IN std_logic;
AOUT : OUT std_logic;
BIN : IN std_logic;
BOUT : OUT std_logic;
CIN : IN std_logic;
COUT : OUT std_logic;
SUMIN : IN std_logic;
SUMOUT : OUT std_logic
); END COMPONENT;
COMPONENT MCELL51
PORT (
AIN : IN std_logic;
AOUT : OUT std_logic;
BIN : IN std_logic;
BOUT : OUT std_logic;
CIN : IN std_logic;
COUT : OUT std_logic;
SUMIN : IN std_logic;
SUMOUT : OUT std_logic
); END COMPONENT;
COMPONENT MCELL61
PORT (
AIN : IN std_logic;
AOUT : OUT std_logic;
BIN : IN std_logic;
BOUT : OUT std_logic;
CIN : IN std_logic;
COUT : OUT std_logic;
SUMIN : IN std_logic;
SUMOUT : OUT std_logic
); END COMPONENT;
COMPONENT MCELL71
PORT (
AIN : IN std_logic;
AOUT : OUT std_logic;
BIN : IN std_logic;
BOUT : OUT std_logic;
CIN : IN std_logic;
COUT : OUT std_logic;
SUMIN : IN std_logic;
SUMOUT : OUT std_logic
); END COMPONENT;
COMPONENT MCELL22
PORT (
AIN : IN std_logic;
AOUT : OUT std_logic;
BIN : IN std_logic;
BOUT : OUT std_logic;
CIN : IN std_logic;
COUT : OUT std_logic;
SUMIN : IN std_logic;
SUMOUT : OUT std_logic
); END COMPONENT;
COMPONENT MCELL24
PORT (
AIN : IN std_logic;
AOUT : OUT std_logic;
BIN : IN std_logic;
BOUT : OUT std_logic;
CIN : IN std_logic;
COUT : OUT std_logic;
SUMIN : IN std_logic;
SUMOUT : OUT std_logic
); END COMPONENT;
COMPONENT MCELL26
PORT (
AIN : IN std_logic;
AOUT : OUT std_logic;
BIN : IN std_logic;
BOUT : OUT std_logic;
CIN : IN std_logic;
COUT : OUT std_logic;
SUMIN : IN std_logic;
SUMOUT : OUT std_logic
); END COMPONENT;
COMPONENT MCELL28
PORT (
AIN : IN std_logic;
AOUT : OUT std_logic;
BIN : IN std_logic;
BOUT : OUT std_logic;
CIN : IN std_logic;
COUT : OUT std_logic;
SUMIN : IN std_logic;
SUMOUT : OUT std_logic
); END COMPONENT;
COMPONENT MCELL210
PORT (
AIN : IN std_logic;
AOUT : OUT std_logic;
BIN : IN std_logic;
BOUT : OUT std_logic;
CIN : IN std_logic;
COUT : OUT std_logic;
SUMIN : IN std_logic;
SUMOUT : OUT std_logic
); END COMPONENT;
COMPONENT MCELL212
PORT (
AIN : IN std_logic;
AOUT : OUT std_logic;
BIN : IN std_logic;
BOUT : OUT std_logic;
CIN : IN std_logic;
COUT : OUT std_logic;
SUMIN : IN std_logic;
SUMOUT : OUT std_logic
); END COMPONENT;
COMPONENT MCELL214
PORT (
AIN : IN std_logic;
AOUT : OUT std_logic;
BIN : IN std_logic;
BOUT : OUT std_logic;
CIN : IN std_logic;
COUT : OUT std_logic;
SUMIN : IN std_logic;
SUMOUT : OUT std_logic
); END COMPONENT;
-- SIGNALS
SIGNAL TEST88 : std_logic;
SIGNAL TEST89 : std_logic;
SIGNAL TEST90 : std_logic;
SIGNAL TEST91 : std_logic;
SIGNAL TEST92 : std_logic;
SIGNAL TEST94 : std_logic;
SIGNAL TEST95 : std_logic;
SIGNAL TEST96 : std_logic;
SIGNAL TEST97 : std_logic;
SIGNAL TEST98 : std_logic;
SIGNAL TEST99 : std_logic;
SIGNAL TEST100 : std_logic;
SIGNAL TEST101 : std_logic;
SIGNAL TEST102 : std_logic;
SIGNAL TEST103 : std_logic;
SIGNAL TEST104 : std_logic;
SIGNAL TEST105 : std_logic;
SIGNAL TEST106 : std_logic;
SIGNAL TEST107 : std_logic;
SIGNAL TEST108 : std_logic;
SIGNAL TEST109 : std_logic;
SIGNAL TEST110 : std_logic;
SIGNAL TEST111 : std_logic;
SIGNAL TEST93 : std_logic;
SIGNAL TEST112 : std_logic;
SIGNAL TEST113 : std_logic;
SIGNAL TEST114 : std_logic;
SIGNAL TEST115 : std_logic;
SIGNAL TEST116 : std_logic;
SIGNAL TEST117 : std_logic;
SIGNAL N23528 : std_logic;
SIGNAL N23080 : std_logic;
SIGNAL N23188 : std_logic;
SIGNAL N23512 : std_logic;
SIGNAL N23100 : std_logic;
SIGNAL N23092 : std_logic;
SIGNAL N22676 : std_logic;
SIGNAL N28640 : std_logic;
SIGNAL N10645 : std_logic;
SIGNAL N10543 : std_logic;
SIGNAL N09859 : std_logic;
SIGNAL N09910 : std_logic;
SIGNAL N181410 : std_logic;
SIGNAL N10077 : std_logic;
SIGNAL N10390 : std_logic;
SIGNAL N22624 : std_logic;
SIGNAL N28815 : std_logic;
SIGNAL N23152 : std_logic;
SIGNAL N23192 : std_logic;
SIGNAL N23084 : std_logic;
SIGNAL N22808 : std_logic;
SIGNAL N22680 : std_logic;
SIGNAL N23164 : std_logic;
SIGNAL N23264 : std_logic;
SIGNAL N23088 : std_logic;
SIGNAL N10128 : std_logic;
SIGNAL N28980 : std_logic;
SIGNAL N10237 : std_logic;
SIGNAL N08574 : std_logic;
SIGNAL N08683 : std_logic;
SIGNAL N08348 : std_logic;
SIGNAL N33821 : std_logic;
SIGNAL N33872 : std_logic;
SIGNAL N26020 : std_logic;
SIGNAL N33923 : std_logic;
SIGNAL N25628 : std_logic;
SIGNAL N33974 : std_logic;
SIGNAL N35622 : std_logic;
SIGNAL N24088 : std_logic;
SIGNAL N34429 : std_logic;
SIGNAL N24484 : std_logic;
SIGNAL N34737 : std_logic;
SIGNAL N295285 : std_logic;
SIGNAL N24944 : std_logic;
SIGNAL N24180 : std_logic;
SIGNAL N24164 : std_logic;
SIGNAL N24836 : std_logic;
SIGNAL N35480 : std_logic;
SIGNAL N26232 : std_logic;
SIGNAL N25684 : std_logic;
SIGNAL N26348 : std_logic;
SIGNAL N26480 : std_logic;
SIGNAL N25716 : std_logic;
SIGNAL N26376 : std_logic;
SIGNAL N26004 : std_logic;
SIGNAL N25680 : std_logic;
SIGNAL N25696 : std_logic;
SIGNAL N26364 : std_logic;
SIGNAL N24204 : std_logic;
SIGNAL N35035 : std_logic;
SIGNAL N24840 : std_logic;
SIGNAL N24224 : std_logic;
SIGNAL N24468 : std_logic;
SIGNAL N24144 : std_logic;
SIGNAL N39255 : std_logic;
SIGNAL N24820 : std_logic;
SIGNAL N39228 : std_logic;
SIGNAL N24948 : std_logic;
SIGNAL N24208 : std_logic;
SIGNAL N24832 : std_logic;
SIGNAL N24488 : std_logic;
SIGNAL N39201 : std_logic;
SIGNAL N26288 : std_logic;
SIGNAL N39174 : std_logic;
SIGNAL N35137 : std_logic;
SIGNAL N39147 : std_logic;
SIGNAL N25880 : std_logic;
SIGNAL N26356 : std_logic;
SIGNAL N26484 : std_logic;
SIGNAL N39120 : std_logic;
SIGNAL N25744 : std_logic;
SIGNAL N38904 : std_logic;
SIGNAL N10441 : std_logic;
SIGNAL N38931 : std_logic;
SIGNAL N09687 : std_logic;
SIGNAL N08025 : std_logic;
SIGNAL N08427 : std_logic;
SIGNAL N38958 : std_logic;
SIGNAL N08762 : std_logic;
SIGNAL N38985 : std_logic;
SIGNAL N25624 : std_logic;
SIGNAL N34025 : std_logic;
SIGNAL N25700 : std_logic;
SIGNAL N179382 : std_logic;
SIGNAL N39012 : std_logic;
SIGNAL N25740 : std_logic;
SIGNAL N25760 : std_logic;
SIGNAL N39039 : std_logic;
SIGNAL N26368 : std_logic;
SIGNAL N39093 : std_logic;
SIGNAL N39066 : std_logic;
SIGNAL N26024 : std_logic;
SIGNAL N23252 : std_logic;
SIGNAL N23076 : std_logic;
SIGNAL N13556 : std_logic;
SIGNAL N28498 : std_logic;
SIGNAL N11218 : std_logic;
SIGNAL N11371 : std_logic;
SIGNAL N11116 : std_logic;
SIGNAL N11320 : std_logic;
SIGNAL N38601 : std_logic;
SIGNAL N10963 : std_logic;
SIGNAL N11065 : std_logic;
SIGNAL N24092 : std_logic;
SIGNAL N24148 : std_logic;
SIGNAL N24160 : std_logic;
SIGNAL GND : std_logic;
SIGNAL N39282 : std_logic;
SIGNAL N24344 : std_logic;
SIGNAL N22860 : std_logic;
SIGNAL N23336 : std_logic;
SIGNAL N23172 : std_logic;
SIGNAL N23180 : std_logic;
SIGNAL TEST1 : std_logic;
SIGNAL TEST2 : std_logic;
SIGNAL TEST3 : std_logic;
SIGNAL TEST4 : std_logic;
SIGNAL TEST5 : std_logic;
SIGNAL TEST6 : std_logic;
SIGNAL TEST7 : std_logic;
SIGNAL TEST8 : std_logic;
SIGNAL TEST9 : std_logic;
SIGNAL TEST10 : std_logic;
SIGNAL TEST11 : std_logic;
SIGNAL TEST12 : std_logic;
SIGNAL TEST13 : std_logic;
SIGNAL TEST14 : std_logic;
SIGNAL TEST15 : std_logic;
SIGNAL TEST17 : std_logic;
SIGNAL TEST18 : std_logic;
SIGNAL TEST19 : std_logic;
SIGNAL TEST20 : std_logic;
SIGNAL TEST21 : std_logic;
SIGNAL TEST22 : std_logic;
SIGNAL TEST23 : std_logic;
SIGNAL TEST24 : std_logic;
SIGNAL TEST16 : std_logic;
SIGNAL TEST0 : std_logic;
SIGNAL TEST25 : std_logic;
SIGNAL TEST26 : std_logic;
SIGNAL TEST27 : std_logic;
SIGNAL TEST28 : std_logic;
SIGNAL TEST29 : std_logic;
SIGNAL TEST30 : std_logic;
SIGNAL TEST31 : std_logic;
SIGNAL TEST32 : std_logic;
SIGNAL TEST33 : std_logic;
SIGNAL TEST34 : std_logic;
SIGNAL TEST35 : std_logic;
SIGNAL TEST36 : std_logic;
SIGNAL TEST37 : std_logic;
SIGNAL TEST38 : std_logic;
SIGNAL TEST39 : std_logic;
SIGNAL TEST40 : std_logic;
SIGNAL TEST41 : std_logic;
SIGNAL TEST42 : std_logic;
SIGNAL TEST43 : std_logic;
SIGNAL TEST44 : std_logic;
SIGNAL TEST45 : std_logic;
SIGNAL TEST46 : std_logic;
SIGNAL TEST47 : std_logic;
SIGNAL TEST48 : std_logic;
SIGNAL TEST49 : std_logic;
SIGNAL TEST50 : std_logic;
SIGNAL TEST51 : std_logic;
SIGNAL TEST52 : std_logic;
SIGNAL TEST53 : std_logic;
SIGNAL TEST54 : std_logic;
SIGNAL TEST56 : std_logic;
SIGNAL TEST55 : std_logic;
SIGNAL TEST57 : std_logic;
SIGNAL TEST58 : std_logic;
SIGNAL TEST59 : std_logic;
SIGNAL TEST60 : std_logic;
SIGNAL TEST61 : std_logic;
SIGNAL TEST62 : std_logic;
SIGNAL TEST63 : std_logic;
SIGNAL TEST64 : std_logic;
SIGNAL TEST65 : std_logic;
SIGNAL TEST66 : std_logic;
SIGNAL TEST67 : std_logic;
SIGNAL TEST68 : std_logic;
SIGNAL TEST69 : std_logic;
SIGNAL TEST70 : std_logic;
SIGNAL TEST71 : std_logic;
SIGNAL TEST72 : std_logic;
SIGNAL TEST73 : std_logic;
SIGNAL TEST74 : std_logic;
SIGNAL TEST75 : std_logic;
SIGNAL TEST76 : std_logic;
SIGNAL TEST77 : std_logic;
SIGNAL TEST78 : std_logic;
SIGNAL TEST79 : std_logic;
SIGNAL TEST80 : std_logic;
SIGNAL TEST81 : std_logic;
SIGNAL TEST82 : std_logic;
SIGNAL TEST83 : std_logic;
SIGNAL TEST84 : std_logic;
SIGNAL TEST85 : std_logic;
SIGNAL TEST86 : std_logic;
SIGNAL TEST87 : std_logic;
-- GATE INSTANCES
BEGIN
GND <= '0';
U330 : MCELL21 PORT MAP(
AIN => N35035,
AOUT => N25696,
BIN => N26364,
BOUT => N26288,
CIN => TEST96,
COUT => TEST98,
SUMIN => TEST84,
SUMOUT => TEST97
);
U331 : MCELL21 PORT MAP(
AIN => N24224,
AOUT => N35035,
BIN => N24204,
BOUT => N24832,
CIN => TEST94,
COUT => TEST96,
SUMIN => TEST82,
SUMOUT => TEST95
);
U332 : MCELL21 PORT MAP(
AIN => N24144,
AOUT => N24224,
BIN => N24840,
BOUT => N24948,
CIN => TEST92,
COUT => TEST94,
SUMIN => TEST80,
SUMOUT => TEST93
);
U300 : MCELL21 PORT MAP(
AIN => N10543,
AOUT => N10441,
BIN => N11320,
BOUT => N09859,
CIN => TEST25,
COUT => TEST27,
SUMIN => TEST14,
SUMOUT => TEST26
);
U333 : MCELL21 PORT MAP(
AIN => N24160,
AOUT => N24144,
BIN => N24468,
BOUT => N24820,
CIN => TEST90,
COUT => TEST92,
SUMIN => TEST78,
SUMOUT => TEST91
);
U302 : MCELL21 PORT MAP(
AIN => N181410,
AOUT => N08025,
BIN => N09859,
BOUT => N08348,
CIN => TEST40,
COUT => TEST42,
SUMIN => TEST28,
SUMOUT => TEST41
);
U334 : MCELL21 PORT MAP(
AIN => N24344,
AOUT => N24208,
BIN => N24820,
BOUT => N39255,
CIN => TEST105,
COUT => TEST106,
SUMIN => TEST93,
SUMOUT => Y8
);
U303 : MCELL21 PORT MAP(
AIN => N10390,
AOUT => N181410,
BIN => N09910,
BOUT => N08574,
CIN => TEST38,
COUT => TEST40,
SUMIN => TEST26,
SUMOUT => TEST39
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