pci_top.v

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// --------------------------------------------------------------------
// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// --------------------------------------------------------------------
// Copyright (c) 2001 by Lattice Semiconductor Corporation
// --------------------------------------------------------------------
//
// Permission:
//
//   Lattice Semiconductor grants permission to use this code for use
//   in synthesis for any Lattice programmable logic product.  Other
//   use of this code, including the selling or duplication of any
//   portion is strictly prohibited.
//
// Disclaimer:
//
//   This VHDL or Verilog source code is intended as a design reference
//   which illustrates how these types of functions can be implemented.
//   It is the user's responsibility to verify their design for
//   consistency and functionality through the use of formal
//   verification methods.  Lattice Semiconductor provides no warranty
//   regarding the use or functionality of this code.
//
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//                     Lattice Semiconductor Corporation
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// Revision History :
// --------------------------------------------------------------------
//   Ver  :| Author            :| Mod. Date :| Changes Made:
//   v1.0 :| D.S.              :| 12/15/98  :| Initial Creation
//   v1.1 :| D.S.              :| 10/05/99  :| added be_oe     
// --------------------------------------------------------------------
//
//	Module  pci_top
//
//  This block is the top level Verilog module for the Vantis 32 bit 33Mhz
//  PCI Target Reference Design.  It instantiates the following modules:
//    - state_machine.v
//    - pargen.v
//    - config_mux.v
//    - base_addr_chk.v
//  It also creates the I/O ring for this device (Tri-state buffers) and the
//  pci_addr register
//
//  TO configure this Reference Design the Engineer will need to modify the
//  parameters in config_mux to the requirements of the backend device.
//
//  Current implementation requires 111 I/O's
//


module pci_top        ( pci_ad, pci_cbe_l, pci_par, pci_frame_l, pci_trdy_l,
                        pci_irdy_l, pci_stop_l, pci_devsel_l, pci_idsel,
			pci_clk, pci_rst_l, pci_inta_l,
			bkend_ad, bkend_dat, be_l, base_region0_l,
			base_region1_l, ready_l, r_w_l, data_write_l,
			data_read_l, data_stop_l, bkend_int_l, 
			bkend_abort_l);

/*******************************/  
/**** PCI Target interface *****/
/*******************************/

inout [31:0] pci_ad;
input [3:0] pci_cbe_l;
output pci_par;
input pci_frame_l;
output pci_trdy_l;
input pci_irdy_l;
output pci_stop_l;
output pci_devsel_l;
input pci_idsel;
input pci_clk;
input pci_rst_l;
output pci_inta_l;

/********************************/
/*** Backend interface signals **/
/********************************/

output [19:0] bkend_ad; // back end address lines; These can be sized.
inout [31:0] bkend_dat;
output [3:0] be_l;
output base_region0_l;
output base_region1_l;
input ready_l;
output r_w_l;
output data_write_l;
output data_read_l;
input data_stop_l;
input bkend_int_l;
input bkend_abort_l;

/*********************************************/
/*  Internal Wire Declarations               */
/*********************************************/

wire pci_ad_oe, par_oe, dts_oe, bk_oe;
wire hit_ba0_l, hit_ba1_l;
wire [31:4] ba0_size;
wire [31:4] ba1_size;
wire ba0_en, ba1_en;
wire devsel_l, trdy_l, stop_l, par_out;
wire [31:0] pci_dat_out;
wire pci_ad_en;
wire abort_sig;
wire [1:0] com;
wire retry_l, count_rst_l, count_en_l;
wire [31:0] pci_addr;
wire data_read_l;
wire [3:0] cbe_reg_l;
wire be_oe;

/************************************************/
/** Start of I/O Ring & Glue Logic section   ***/
/***********************************************/

assign pci_ad = pci_ad_oe ? pci_dat_out : 32'bZ; 
assign pci_devsel_l = dts_oe ? devsel_l : 1'bZ;
assign pci_trdy_l = dts_oe ? trdy_l : 1'bZ;
assign pci_stop_l = dts_oe ? stop_l : 1'bZ;
assign pci_par = par_oe ? par_out : 1'bZ; // The parity bit  the target drives
assign bkend_dat = bk_oe ? pci_ad : 32'bZ; 
assign be_l = be_oe ? pci_cbe_l: 4'bZ;
assign pci_inta_l = bkend_int_l; // asynchronous input is passed through
assign bkend_ad = pci_addr[19:0];

glue glue1 ( .pci_clk(pci_clk),
             .pci_rst_l(pci_rst_l),
	     .pci_ad_en(pci_ad_en),
	     .pci_ad(pci_ad),
	     .pci_addr(pci_addr),
	     .pci_cbe_l(pci_cbe_l),
	     .pci_idsel(pci_idsel),
	     .idsel_reg(idsel_reg),
	     .cbe_reg_l(cbe_reg_l)
	    );

/************************************************/
/** End of I/O Ring & Glue Logic section   *****/
/***********************************************/


/**************************************************/
/** Start State Machine Instantiation section   ***/
/**************************************************/


state_machine smcn (.devsel_l(devsel_l), 
		    .trdy_l(trdy_l), 
                    .stop_l(stop_l), 
		    .pci_ad_oe(pci_ad_oe), 
		    .dts_oe(dts_oe), 
		    .par_oe(par_oe), 
		    .bk_oe(bk_oe), 
		    .pci_ad_en(pci_ad_en), 
		    .hit_ba0_l(hit_ba0_l), 
		    .hit_ba1_l(hit_ba1_l), 
		    .pci_frame_l(pci_frame_l), 
		    .pci_idsel(pci_idsel), 
		    .pci_irdy_l(pci_irdy_l), 
		    .pci_ad(pci_ad),
                    .pci_cbe_l(pci_cbe_l),
		    .pci_clk(pci_clk),
		    .pci_rst_l(pci_rst_l), 
		    .abort_sig(abort_sig), 
		    .data_stop_l(data_stop_l), 
                    .data_write_l(data_write_l), 
		    .ready_l(ready_l), 
		    .bkend_abort_l(bkend_abort_l),
		    .com(com),
		    .count_rst_l(count_rst_l), 
	            .count_en_l(count_en_l), 
	            .retry_l(retry_l),
		    .base_region0_l(base_region0_l),
                    .base_region1_l(base_region1_l),
		    .r_w_l(r_w_l),
		    .data_read_l(data_read_l),
		    .be_oe(be_oe)
                    );


/**************************************************/
/** End State Machine Instantiation section   *****/
/**************************************************/

/******************************************************/
/** Start retry_count Instantiation section         ***/
/******************************************************/


retry_count  retry_count1 (.pci_clk(pci_clk), 
                           .count_rst_l(count_rst_l), 
			   .count_en_l(count_en_l), 
			   .retry_l(retry_l)
			   );


/******************************************************/
/** End  retry_count Instantiation section        *****/
/******************************************************/




/******************************************************/
/** Start Parity Generation Instantiation section   ***/
/******************************************************/


pargen pargen1 (.par_out(par_out), 
                .pci_cbe_l(pci_cbe_l), 
		.pci_dat_out(pci_dat_out), 
		.pci_clk(pci_clk),
		.par_oe(par_oe)
                );


/******************************************************/
/** End Parity Generation Instantiation section   *****/
/******************************************************/


/******************************************************/
/** Start config_mux Instantiation section        *****/
/** This block contains the majority of the PCI   *****/
/** Configuration Registers, and the output       *****/
/** data mux for the pci data bus.                *****/
/** The Engineer should set the appropriate       *****/
/** parameters in the config_mux block.           *****/
/******************************************************/


config_mux con_mux (.pci_dat_out(pci_dat_out), 
                    .ba0_size(ba0_size), 
		    .ba1_size(ba1_size), 
		    .bkend_dat(bkend_dat), 
                    .pci_dat(pci_ad), // the raw pci data 
		    .pci_cbe_l(pci_cbe_l), 
		    .pci_rst_l(pci_rst_l),
		    .abort_sig(abort_sig), 
		    .pci_clk(pci_clk),
		    .com(com),
		    .ba0_en(ba0_en),
		    .ba1_en(ba1_en),
		    .cbe_reg_l(cbe_reg_l),
		    .idsel_reg(idsel_reg),
		    .pci_addr(pci_addr[7:0]),
		    .pci_irdy_l(pci_irdy_l)
		    );
 

/******************************************************/
/**   End config_mux Instantiation section        *****/
/******************************************************/



/******************************************************/
/** Start base_addr_chk Instantiation section       ***/
/** Decodes ifs the address on the PCI bus is       ***/
/** accessing the backend device                    ***/
/******************************************************/

base_addr_chk  bachk (.hit_ba0_l(hit_ba0_l), 
                      .hit_ba1_l(hit_ba1_l), 
		      .ba0_size(ba0_size), 
                      .ba1_size(ba1_size),
 		      .pci_ad(pci_ad[31:4]), // raw pci data
		      .pci_addr(pci_addr[31:4]), // reg'd pci addr
		      .ba0_en(ba0_en), 
		      .ba1_en(ba1_en), 
		      .pci_clk(pci_clk), 
		      .pci_rst_l(pci_rst_l)
		      );

/******************************************************/
/** End base_addr_chk Instantiation section       *****/
/******************************************************/

endmodule // of pci_top