testp1.scr

cadence公司pcb内部培训的资料,并且附带其中的例子程序!比市面上任何一本cadence的书好!

# Allegro script
#	file: D:\Develop\PSD140\140AdvancedAllegro\6LabTestPrep\testp1.scr
#	start time: Mon Feb 05 16:30:03 2001
version 14.0

setwindow pcb

color 
setwindow form.cvf_main
FORM cvf_main class_list Stack-Up
FORM cvf_main class_list Manufacturing 
FORM cvf_main manufacturing/probe_top/visible YES 
FORM cvf_main manufacturing/probe_bottom/visible YES 
FORM cvf_main color7 6 
FORM cvf_main manufacturing/probe_top/color 7 
FORM cvf_main color19 18 
FORM cvf_main manufacturing/probe_bottom/color 19 
FORM cvf_main ok  
setwindow pcb
status 
setwindow form.status
FORM status display  
FORM status display_enhance NO 
FORM status done  
setwindow pcb
testprep param 
setwindow form.probe_info
FORM probe_info test_pin_type Any Pin 
FORM probe_info test_pad_type Either 
FORM probe_info layer_to_test Either 
FORM probe_info test_method Flood 
FORM probe_info bare_board_test YES 
FORM probe_info test_unused_pins YES 
FORM probe_info allow_under_comp YES 
FORM probe_info text_info_button  
setwindow form.probe_text
FORM probe_text done  
setwindow form.probe_info
FORM probe_info text_info_button  
setwindow form.probe_text
FORM probe_text display_text NO 
FORM probe_text done  
setwindow form.probe_info
FORM probe_info done  
setwindow pcb
testprep execute 
zoom points 
drag_start 2764.18 1490.25
drag_stop 1917.53 2368.55
roam start
roam x 16
roam x 16
roam x 16
roam x 16
roam x 16
roam x 16
roam x 16
roam x 16
roam x 16
roam y -16
roam y -16
roam y -16
roam y -32
roam y -16
roam y -16
roam y -16
roam y -16
roam y -16
roam y -16
roam y -32
roam y -16
roam x -16
roam y 16
roam y 16
roam x -16
roam y 16
roam y 16
roam x -16
roam y 16
roam y 16
roam x -16
roam y 16
roam y 16
roam y 16
roam end
roam start
roam y 16
roam y 32
roam y 16
roam y 16
roam y 16
roam y 16
roam y 16
roam y 16
roam x 16
roam y 16
roam y 16
roam y 16
roam y 16
roam y 16
roam y 16
roam y 16
roam end
viewlog -last 
setwindow text
close 
setwindow pcb
testprep param 
setwindow form.probe_info
FORM probe_info test_pin_type Via 
FORM probe_info test_pad_type Thru 
FORM probe_info layer_to_test Bottom 
FORM probe_info test_method Single 
FORM probe_info bare_board_test NO 
FORM probe_info test_unused_pins NO 
FORM probe_info min_test_pad_size 20 
FORM probe_info min_test_spacing 50 
FORM probe_info allow_under_comp NO 
FORM probe_info done  
setwindow pcb
testprep execute 
testprep param 
setwindow form.probe_info
FORM probe_info test_pin_type Any Pnt 
FORM probe_info test_via_browse  
fillin "Via"
FORM probe_info allow_auto_insert YES 
FORM probe_info execute_increment YES 
FORM probe_info max_test_displace 500 
FORM probe_info done  
setwindow pcb
testprep execute 

#	stop time: Mon Feb 05 16:34:50 2001