hdldirect.dat

cadence公司pcb内部培训的资料,并且附带其中的例子程序!比市面上任何一本cadence的书好!

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 (design_name "root" )
 (view "sch_1" )
 (modtime "verilog.v" 1020258273 5584 )
 (timescale "1ns/1ns" )
 (cells "CAP_NP" "TC55B4257" )
 (global_signals 
  ("glbl" "GND" "STD_LOGIC" "supply0" "" "" )
  ("glbl" "VCC" "STD_LOGIC" "supply1" "" "" ))
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   ("page1_I174" "CAP_NP" )
   ("page1_I175" "CAP_NP" )
   ("page1_I176" "CAP_NP" )
   ("page2_I1" "TC55B4257" )
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   ("page2_I27" "TC55B4257" )
   ("page2_I53" "TC55B4257" )
   ("page2_I89" "CAP_NP" )
   ("page2_I90" "CAP_NP" )
   ("page2_I91" "CAP_NP" )
   ("page2_I92" "CAP_NP" )))
 (multiple_pages ))