pstxprt.dat

cadence公司pcb内部培训的资料,并且附带其中的例子程序!比市面上任何一本cadence的书好!

FILE_TYPE=EXPANDEDPARTLIST;
{ Packager-XL run on 01-May-2002 AT 09:01:13 }
DIRECTIVES
 PST_VERSION='PST_HDL_CENTRIC_VERSION_0';
 ROOT_DRAWING='ROOT';
 POST_TIME='01-May-2002 AT 09:01:13';
 SOURCE_TOOL='PACKAGER_XL';
END_DIRECTIVES;

PART_NAME
 C1 'CAP_NP_SMDCAP-.1UF,+20%/-80%':;

SECTION_NUMBER 1
 '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]_NP(CHIPS)':
 C_PATH='@project1_lib.root(sch_1):[e-mail]_np(chips)',
 PATH='I9',
 DRAWING='@PROJECT1_LIB.ROOT(SCH_1):PAGE1',
 XY='(-3500,1400)',
 VER='2',
 ROT='0',
 TOLERENCE='+20%/-80%',
 VALUE='.1UF',
 CDS_LIB='classlib',
 PACK_TYPE='SMDCAP',
 PRIM_FILE='./classlib/cap_np/chips/chips.prt';

PART_NAME
 C2 'CAP_NP_SMDCAP-.1UF,+20%/-80%':;

SECTION_NUMBER 1
 '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]_NP(CHIPS)':
 C_PATH='@project1_lib.root(sch_1):[e-mail]_np(chips)',
 PATH='I15',
 DRAWING='@PROJECT1_LIB.ROOT(SCH_1):PAGE1',
 XY='(-3000,1400)',
 VER='2',
 ROT='0',
 VALUE='.1UF',
 TOLERENCE='+20%/-80%',
 CDS_LIB='classlib',
 PACK_TYPE='SMDCAP',
 PRIM_FILE='./classlib/cap_np/chips/chips.prt';

PART_NAME
 C3 'CAP_NP_SMDCAP-.1UF,+20%/-80%':;

SECTION_NUMBER 1
 '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]_NP(CHIPS)':
 C_PATH='@project1_lib.root(sch_1):[e-mail]_np(chips)',
 PATH='I16',
 DRAWING='@PROJECT1_LIB.ROOT(SCH_1):PAGE1',
 XY='(-2500,1400)',
 VER='2',
 ROT='0',
 TOLERENCE='+20%/-80%',
 VALUE='.1UF',
 CDS_LIB='classlib',
 PACK_TYPE='SMDCAP',
 PRIM_FILE='./classlib/cap_np/chips/chips.prt';

PART_NAME
 C4 'CAP_NP_SMDCAP-.1UF,+20%/-80%':;

SECTION_NUMBER 1
 '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]_NP(CHIPS)':
 C_PATH='@project1_lib.root(sch_1):[e-mail]_np(chips)',
 PATH='I17',
 DRAWING='@PROJECT1_LIB.ROOT(SCH_1):PAGE1',
 XY='(-2000,1400)',
 VER='2',
 ROT='0',
 VALUE='.1UF',
 TOLERENCE='+20%/-80%',
 PACK_TYPE='SMDCAP',
 CDS_LIB='classlib',
 PRIM_FILE='./classlib/cap_np/chips/chips.prt';

PART_NAME
 C5 'CAP_SMDCAP-47PF,10%':
 ROOM='CHAN1';

SECTION_NUMBER 1
 '@PROJECT1_LIB.ROOT(SCH_1):[e-mail](CHIPS)':
 C_PATH='@project1_lib.root(sch_1):[e-mail](chips)',
 PATH='I3',
 DRAWING='@PROJECT1_LIB.ROOT(SCH_1):PAGE2',
 ROOM='CHAN1',
 XY='(1100,2000)',
 VER='2',
 ROT='0',
 TOLERENCE='10%',
 VALUE='47PF',
 PACK_TYPE='SMDCAP',
 CDS_LIB='classlib',
 PRIM_FILE='./classlib/cap/chips/chips.prt';

PART_NAME
 C6 'CAP_SMDCAP-47PF,10%':
 ROOM='CHAN2';

SECTION_NUMBER 1
 '@PROJECT1_LIB.ROOT(SCH_1):[e-mail](CHIPS)':
 C_PATH='@project1_lib.root(sch_1):[e-mail](chips)',
 PATH='I4',
 DRAWING='@PROJECT1_LIB.ROOT(SCH_1):PAGE2',
 ROOM='CHAN2',
 XY='(1100,1300)',
 VER='2',
 ROT='0',
 VALUE='47PF',
 TOLERENCE='10%',
 PACK_TYPE='SMDCAP',
 CDS_LIB='classlib',
 PRIM_FILE='./classlib/cap/chips/chips.prt';

PART_NAME
 C7 'CAP_SMDCAP-3300PF,10%':;

SECTION_NUMBER 1
 '@PROJECT1_LIB.ROOT(SCH_1):PAGE2_I20@PROJECT1_LIB.DATA(SCH_1):[e-mail](CHIPS)':
 C_PATH='@project1_lib.root(sch_1):page2_i20@project1_lib.data(sch_1):page1_i12@~
classlib.cap(chips)',
 PATH='I12',
 DRAWING='@PROJECT1_LIB.DATA(SCH_1):PAGE1',
 XY='(300,3850)',
 VER='2',
 ROT='0',
 TOLERENCE='10%',
 VALUE='3300PF',
 LOCATION='C7',
 CDS_LIB='classlib',
 PACK_TYPE='SMDCAP',
 USE2='work.all',
 USE1='ieee.std_logic_1164.all',
 LIBRARY1='ieee',
 PRIM_FILE='./classlib/cap/chips/chips.prt';

PART_NAME
 C8 'CAP_SMDCAP-3300PF,10%':;

SECTION_NUMBER 1
 '@PROJECT1_LIB.ROOT(SCH_1):PAGE2_I20@PROJECT1_LIB.DATA(SCH_1):[e-mail](CHIPS)':
 C_PATH='@project1_lib.root(sch_1):page2_i20@project1_lib.data(sch_1):page1_i14@~
classlib.cap(chips)',
 PATH='I14',
 DRAWING='@PROJECT1_LIB.DATA(SCH_1):PAGE1',
 XY='(1000,3850)',
 VER='2',
 ROT='0',
 TOLERENCE='10%',
 VALUE='3300PF',
 LOCATION='C8',
 CDS_LIB='classlib',
 PACK_TYPE='SMDCAP',
 USE2='work.all',
 USE1='ieee.std_logic_1164.all',
 LIBRARY1='ieee',
 PRIM_FILE='./classlib/cap/chips/chips.prt';

PART_NAME
 C9 'CAP_SMDCAP-3300PF,10%':;

SECTION_NUMBER 1
 '@PROJECT1_LIB.ROOT(SCH_1):PAGE2_I20@PROJECT1_LIB.DATA(SCH_1):[e-mail](CHIPS)':
 C_PATH='@project1_lib.root(sch_1):page2_i20@project1_lib.data(sch_1):page1_i16@~
classlib.cap(chips)',
 PATH='I16',
 DRAWING='@PROJECT1_LIB.DATA(SCH_1):PAGE1',
 XY='(1700,3850)',
 VER='2',
 ROT='0',
 TOLERENCE='10%',
 VALUE='3300PF',
 LOCATION='C9',
 CDS_LIB='classlib',
 PACK_TYPE='SMDCAP',
 USE2='work.all',
 USE1='ieee.std_logic_1164.all',
 LIBRARY1='ieee',
 PRIM_FILE='./classlib/cap/chips/chips.prt';

PART_NAME
 C10 'CAP_SMDCAP-3300PF,10%':;

SECTION_NUMBER 1
 '@PROJECT1_LIB.ROOT(SCH_1):PAGE2_I20@PROJECT1_LIB.DATA(SCH_1):[e-mail](CHIPS)':
 C_PATH='@project1_lib.root(sch_1):page2_i20@project1_lib.data(sch_1):page1_i18@~
classlib.cap(chips)',
 PATH='I18',
 DRAWING='@PROJECT1_LIB.DATA(SCH_1):PAGE1',
 XY='(2400,3850)',
 VER='2',
 ROT='0',
 TOLERENCE='10%',
 VALUE='3300PF',
 LOCATION='C10',
 CDS_LIB='classlib',
 PACK_TYPE='SMDCAP',
 USE2='work.all',
 USE1='ieee.std_logic_1164.all',
 LIBRARY1='ieee',
 PRIM_FILE='./classlib/cap/chips/chips.prt';

PART_NAME
 C11 'CAP_SMDCAP-3300PF,10%':;

SECTION_NUMBER 1
 '@PROJECT1_LIB.ROOT(SCH_1):PAGE2_I20@PROJECT1_LIB.DATA(SCH_1):[e-mail](CHIPS)':
 C_PATH='@project1_lib.root(sch_1):page2_i20@project1_lib.data(sch_1):page1_i11@~
classlib.cap(chips)',
 PATH='I11',
 DRAWING='@PROJECT1_LIB.DATA(SCH_1):PAGE1',
 XY='(-50,3850)',
 VER='2',
 ROT='0',
 VALUE='3300PF',
 TOLERENCE='10%',
 LOCATION='C11',
 CDS_LIB='classlib',
 PACK_TYPE='SMDCAP',
 USE2='work.all',
 USE1='ieee.std_logic_1164.all',
 LIBRARY1='ieee',
 PRIM_FILE='./classlib/cap/chips/chips.prt';

PART_NAME
 C12 'CAP_SMDCAP-3300PF,10%':;

SECTION_NUMBER 1
 '@PROJECT1_LIB.ROOT(SCH_1):PAGE2_I20@PROJECT1_LIB.DATA(SCH_1):[e-mail](CHIPS)':
 C_PATH='@project1_lib.root(sch_1):page2_i20@project1_lib.data(sch_1):page1_i13@~
classlib.cap(chips)',
 PATH='I13',
 DRAWING='@PROJECT1_LIB.DATA(SCH_1):PAGE1',
 XY='(650,3850)',
 VER='2',
 ROT='0',
 TOLERENCE='10%',
 VALUE='3300PF',
 LOCATION='C12',
 CDS_LIB='classlib',
 PACK_TYPE='SMDCAP',
 USE2='work.all',
 USE1='ieee.std_logic_1164.all',
 LIBRARY1='ieee',
 PRIM_FILE='./classlib/cap/chips/chips.prt';

PART_NAME
 C13 'CAP_SMDCAP-3300PF,10%':;

SECTION_NUMBER 1
 '@PROJECT1_LIB.ROOT(SCH_1):PAGE2_I20@PROJECT1_LIB.DATA(SCH_1):[e-mail](CHIPS)':
 C_PATH='@project1_lib.root(sch_1):page2_i20@project1_lib.data(sch_1):page1_i15@~
classlib.cap(chips)',
 PATH='I15',
 DRAWING='@PROJECT1_LIB.DATA(SCH_1):PAGE1',
 XY='(1350,3850)',
 VER='2',
 ROT='0',
 VALUE='3300PF',
 TOLERENCE='10%',
 LOCATION='C13',
 CDS_LIB='classlib',
 PACK_TYPE='SMDCAP',
 USE2='work.all',
 USE1='ieee.std_logic_1164.all',
 LIBRARY1='ieee',
 PRIM_FILE='./classlib/cap/chips/chips.prt';

PART_NAME
 C14 'CAP_SMDCAP-3300PF,10%':;

SECTION_NUMBER 1
 '@PROJECT1_LIB.ROOT(SCH_1):PAGE2_I20@PROJECT1_LIB.DATA(SCH_1):[e-mail](CHIPS)':
 C_PATH='@project1_lib.root(sch_1):page2_i20@project1_lib.data(sch_1):page1_i17@~
classlib.cap(chips)',
 PATH='I17',
 DRAWING='@PROJECT1_LIB.DATA(SCH_1):PAGE1',
 XY='(2050,3850)',
 VER='2',
 ROT='0',
 TOLERENCE='10%',
 VALUE='3300PF',
 LOCATION='C14',
 CDS_LIB='classlib',
 PACK_TYPE='SMDCAP',
 USE2='work.all',
 USE1='ieee.std_logic_1164.all',
 LIBRARY1='ieee',
 PRIM_FILE='./classlib/cap/chips/chips.prt';

PART_NAME
 C15 'CAP_NP_SMDCAP-.1UF,+20%/-80%':
 ROOM='MEM';

SECTION_NUMBER 1
 '@PROJECT1_LIB.ROOT(SCH_1):PAGE2_I19@PROJECT1_LIB.HIGH_SPEED_RAM(SCH_1):[e-mail]_NP(CHIPS)':
 C_PATH='@project1_lib.root(sch_1):page2_i19@project1_lib.high_speed_ram(sch_1):~
[e-mail]_np(chips)',
 PATH='I169',
 DRAWING='@PROJECT1_LIB.HIGH_SPEED_RAM(SCH_1):PAGE1',
 XY='(-1850,550)',
 VER='2',
 ROT='0',
 ROOM='MEM',
 VALUE='.1UF',
 TOLERENCE='+20%/-80%',
 LOCATION='C15',
 CDS_LIB='classlib',
 PACK_TYPE='SMDCAP',
 USE2='work.all',
 USE1='ieee.std_logic_1164.all',
 LIBRARY1='ieee',
 PRIM_FILE='./classlib/cap_np/chips/chips.prt';

PART_NAME
 C16 'CAP_NP_SMDCAP-.1UF,+20%/-80%':
 ROOM='MEM';

SECTION_NUMBER 1
 '@PROJECT1_LIB.ROOT(SCH_1):PAGE2_I19@PROJECT1_LIB.HIGH_SPEED_RAM(SCH_1):[e-mail]_NP(CHIPS)':
 C_PATH='@project1_lib.root(sch_1):page2_i19@project1_lib.high_speed_ram(sch_1):~
[e-mail]_np(chips)',
 PATH='I176',
 DRAWING='@PROJECT1_LIB.HIGH_SPEED_RAM(SCH_1):PAGE1',
 XY='(-1350,550)',
 VER='2',
 ROT='0',
 ROOM='MEM',
 TOLERENCE='+20%/-80%',
 VALUE='.1UF',
 LOCATION='C16',
 PACK_TYPE='SMDCAP',
 CDS_LIB='classlib',
 USE2='work.all',
 USE1='ieee.std_logic_1164.all',
 LIBRARY1='ieee',
 PRIM_FILE='./classlib/cap_np/chips/chips.prt';

PART_NAME
 C17 'CAP_NP_SMDCAP-.1UF,+20%/-80%':
 ROOM='MEM';

SECTION_NUMBER 1
 '@PROJECT1_LIB.ROOT(SCH_1):PAGE2_I19@PROJECT1_LIB.HIGH_SPEED_RAM(SCH_1):[e-mail]_NP(CHIPS)':
 C_PATH='@project1_lib.root(sch_1):page2_i19@project1_lib.high_speed_ram(sch_1):~
[e-mail]_np(chips)',
 PATH='I175',
 DRAWING='@PROJECT1_LIB.HIGH_SPEED_RAM(SCH_1):PAGE1',
 XY='(-850,550)',
 VER='2',
 ROT='0',
 VALUE='.1UF',
 LOCATION='C17',
 TOLERENCE='+20%/-80%',
 ROOM='MEM',
 PACK_TYPE='SMDCAP',
 CDS_LIB='classlib',
 USE2='work.all',
 USE1='ieee.std_logic_1164.all',
 LIBRARY1='ieee',
 PRIM_FILE='./classlib/cap_np/chips/chips.prt';

PART_NAME
 C18 'CAP_NP_SMDCAP-.1UF,+20%/-80%':
 ROOM='MEM';

SECTION_NUMBER 1
 '@PROJECT1_LIB.ROOT(SCH_1):PAGE2_I19@PROJECT1_LIB.HIGH_SPEED_RAM(SCH_1):[e-mail]_NP(CHIPS)':
 C_PATH='@project1_lib.root(sch_1):page2_i19@project1_lib.high_speed_ram(sch_1):~
[e-mail]_np(chips)',
 PATH='I174',
 DRAWING='@PROJECT1_LIB.HIGH_SPEED_RAM(SCH_1):PAGE1',
 XY='(-350,550)',
 VER='2',
 ROT='0',
 VALUE='.1UF',
 LOCATION='C18',
 TOLERENCE='+20%/-80%',
 ROOM='MEM',
 PACK_TYPE='SMDCAP',
 CDS_LIB='classlib',
 USE2='work.all',
 USE1='ieee.std_logic_1164.all',
 LIBRARY1='ieee',
 PRIM_FILE='./classlib/cap_np/chips/chips.prt';

PART_NAME
 C19 'CAP_NP_SMDCAP-.1UF,+20%/-80%':
 ROOM='MEM';

SECTION_NUMBER 1
 '@PROJECT1_LIB.ROOT(SCH_1):PAGE2_I19@PROJECT1_LIB.HIGH_SPEED_RAM(SCH_1):[e-mail]_NP(CHIPS)':
 C_PATH='@project1_lib.root(sch_1):page2_i19@project1_lib.high_speed_ram(sch_1):~
[e-mail]_np(chips)',
 PATH='I92',
 DRAWING='@PROJECT1_LIB.HIGH_SPEED_RAM(SCH_1):PAGE2',
 XY='(-1750,650)',
 VER='2',
 ROT='0',
 ROOM='MEM',
 LOCATION='C19',
 TOLERENCE='+20%/-80%',
 VALUE='.1UF',
 CDS_LIB='classlib',
 PACK_TYPE='SMDCAP',
 USE2='work.all',
 USE1='ieee.std_logic_1164.all',
 LIBRARY1='ieee',
 PRIM_FILE='./classlib/cap_np/chips/chips.prt';

PART_NAME
 C20 'CAP_NP_SMDCAP-.1UF,+20%/-80%':
 ROOM='MEM';

SECTION_NUMBER 1
 '@PROJECT1_LIB.ROOT(SCH_1):PAGE2_I19@PROJECT1_LIB.HIGH_SPEED_RAM(SCH_1):[e-mail]_NP(CHIPS)':
 C_PATH='@project1_lib.root(sch_1):page2_i19@project1_lib.high_speed_ram(sch_1):~
[e-mail]_np(chips)',
 PATH='I91',
 DRAWING='@PROJECT1_LIB.HIGH_SPEED_RAM(SCH_1):PAGE2',
 XY='(-1250,650)',
 VER='2',
 ROT='0',
 ROOM='MEM',
 LOCATION='C20',
 TOLERENCE='+20%/-80%',
 VALUE='.1UF',
 CDS_LIB='classlib',
 PACK_TYPE='SMDCAP',
 USE2='work.all',
 USE1='ieee.std_logic_1164.all',
 LIBRARY1='ieee',
 PRIM_FILE='./classlib/cap_np/chips/chips.prt';

PART_NAME
 C21 'CAP_NP_SMDCAP-.1UF,+20%/-80%':
 ROOM='MEM';

SECTION_NUMBER 1
 '@PROJECT1_LIB.ROOT(SCH_1):PAGE2_I19@PROJECT1_LIB.HIGH_SPEED_RAM(SCH_1):[e-mail]_NP(CHIPS)':
 C_PATH='@project1_lib.root(sch_1):page2_i19@project1_lib.high_speed_ram(sch_1):~
[e-mail]_np(chips)',
 PATH='I90',
 DRAWING='@PROJECT1_LIB.HIGH_SPEED_RAM(SCH_1):PAGE2',
 XY='(-750,650)',
 VER='2',
 ROT='0',
 ROOM='MEM',
 LOCATION='C21',
 VALUE='.1UF',
 TOLERENCE='+20%/-80%',
 CDS_LIB='classlib',
 PACK_TYPE='SMDCAP',
 USE2='work.all',
 USE1='ieee.std_logic_1164.all',
 LIBRARY1='ieee',
 PRIM_FILE='./classlib/cap_np/chips/chips.prt';

PART_NAME
 C22 'CAP_NP_SMDCAP-.1UF,+20%/-80%':
 ROOM='MEM';

SECTION_NUMBER 1
 '@PROJECT1_LIB.ROOT(SCH_1):PAGE2_I19@PROJECT1_LIB.HIGH_SPEED_RAM(SCH_1):[e-mail]_NP(CHIPS)':
 C_PATH='@project1_lib.root(sch_1):page2_i19@project1_lib.high_speed_ram(sch_1):~
[e-mail]_np(chips)',
 PATH='I89',
 DRAWING='@PROJECT1_LIB.HIGH_SPEED_RAM(SCH_1):PAGE2',
 XY='(-250,650)',
 VER='2',
 ROT='0',
 ROOM='MEM',
 LOCATION='C22',
 TOLERENCE='+20%/-80%',
 VALUE='.1UF',
 CDS_LIB='classlib',
 PACK_TYPE='SMDCAP',
 USE2='work.all',
 USE1='ieee.std_logic_1164.all',