pxl.state,1

cadence公司pcb内部培训的资料,并且附带其中的例子程序!比市面上任何一本cadence的书好!

FILE_TYPE = PXL_HDL_CENTRIC_STATE_FILE;
VERSION = PXL_HDL_CENTRIC_VERSION_1;
TIME = '19-Jun-2001 AT 16:09:33.00';

{--------------------------------------------------------------------------}

BEGIN_MODULE: 'ROOT' = '@PROJECT1_LIB.ROOT(SCH_1)';
PAGE = '1';

BEGIN_PRIM:
PATH_NAME  = '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]64(CHIPS)';
LOCATION   = 'J1';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = './classlib/conn64/chips/chips.prt';
 PART_NAME = 'CONN64_PCMOUNT-BASE';
 PARENT_PPT = 'CONN64';
 PARENT_PPT_PART = 'CONN64_PCMOUNT-BASE';
 PARENT_CHIPS_PHYS_PART = 'CONN64_PCMOUNT';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]16245(CHIPS)';
LOCATION   = 'U1';
SEC = '8,7,6,5,4,3,2,1';

BEGIN_LIB_INFO:
 PRIM_FILE = './classlib/fct16245/chips/chips.prt';
 PART_NAME = 'FCT16245_SOIC-BASE';
 PARENT_PPT = 'FCT16245';
 PARENT_PPT_PART = 'FCT16245_SOIC-BASE';
 PARENT_CHIPS_PHYS_PART = 'FCT16245_SOIC';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]16245(CHIPS)';
LOCATION   = 'U3';
SEC = '8,7,6,5,4,3,2,1';

BEGIN_LIB_INFO:
 PRIM_FILE = './classlib/fct16245/chips/chips.prt';
 PART_NAME = 'FCT16245_SOIC-BASE';
 PARENT_PPT = 'FCT16245';
 PARENT_PPT_PART = 'FCT16245_SOIC-BASE';
 PARENT_CHIPS_PHYS_PART = 'FCT16245_SOIC';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]16245(CHIPS)';
LOCATION   = 'U4';
SEC = '8,7,6,5,4,3,2,1';

BEGIN_LIB_INFO:
 PRIM_FILE = './classlib/fct16245/chips/chips.prt';
 PART_NAME = 'FCT16245_SOIC-BASE';
 PARENT_PPT = 'FCT16245';
 PARENT_PPT_PART = 'FCT16245_SOIC-BASE';
 PARENT_CHIPS_PHYS_PART = 'FCT16245_SOIC';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]16245(CHIPS)';
LOCATION   = 'U1';
SEC = '16,15,14,13,12,11,10,9';

BEGIN_LIB_INFO:
 PRIM_FILE = './classlib/fct16245/chips/chips.prt';
 PART_NAME = 'FCT16245_SOIC-BASE';
 PARENT_PPT = 'FCT16245';
 PARENT_PPT_PART = 'FCT16245_SOIC-BASE';
 PARENT_CHIPS_PHYS_PART = 'FCT16245_SOIC';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]16245(CHIPS)';
LOCATION   = 'U3';
SEC = '16,15,14,13,12,11,10,9';

BEGIN_LIB_INFO:
 PRIM_FILE = './classlib/fct16245/chips/chips.prt';
 PART_NAME = 'FCT16245_SOIC-BASE';
 PARENT_PPT = 'FCT16245';
 PARENT_PPT_PART = 'FCT16245_SOIC-BASE';
 PARENT_CHIPS_PHYS_PART = 'FCT16245_SOIC';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]16245(CHIPS)';
LOCATION   = 'U4';
SEC = '16,15,14,13,12,11,10,9';

BEGIN_LIB_INFO:
 PRIM_FILE = './classlib/fct16245/chips/chips.prt';
 PART_NAME = 'FCT16245_SOIC-BASE';
 PARENT_PPT = 'FCT16245';
 PARENT_PPT_PART = 'FCT16245_SOIC-BASE';
 PARENT_CHIPS_PHYS_PART = 'FCT16245_SOIC';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@PROJECT1_LIB.ROOT(SCH_1):PAGE1_I8@CLASSLIB.20L10(CHIPS)';
LOCATION   = 'U2';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = './classlib/20l10/chips/chips.prt';
 PART_NAME = '20L10_DIP-BASE';
 PARENT_PPT = '20L10';
 PARENT_PPT_PART = '20L10_DIP-BASE';
 PARENT_CHIPS_PHYS_PART = '20L10_DIP';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]_NP(CHIPS)';
LOCATION   = 'C1';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = './classlib/cap_np/chips/chips.prt';
 PART_NAME = 'CAP_NP_SMDCAP-.1UF,+20%/-80%';
 PARENT_PPT = 'CAP_NP';
 PARENT_PPT_PART = 'CAP_NP_SMDCAP-.1UF,+20%/-80%';
 PARENT_CHIPS_PHYS_PART = 'CAP_NP_SMDCAP';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]_NP(CHIPS)';
LOCATION   = 'C2';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = './classlib/cap_np/chips/chips.prt';
 PART_NAME = 'CAP_NP_SMDCAP-.1UF,+20%/-80%';
 PARENT_PPT = 'CAP_NP';
 PARENT_PPT_PART = 'CAP_NP_SMDCAP-.1UF,+20%/-80%';
 PARENT_CHIPS_PHYS_PART = 'CAP_NP_SMDCAP';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]_NP(CHIPS)';
LOCATION   = 'C3';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = './classlib/cap_np/chips/chips.prt';
 PART_NAME = 'CAP_NP_SMDCAP-.1UF,+20%/-80%';
 PARENT_PPT = 'CAP_NP';
 PARENT_PPT_PART = 'CAP_NP_SMDCAP-.1UF,+20%/-80%';
 PARENT_CHIPS_PHYS_PART = 'CAP_NP_SMDCAP';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]_NP(CHIPS)';
LOCATION   = 'C4';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = './classlib/cap_np/chips/chips.prt';
 PART_NAME = 'CAP_NP_SMDCAP-.1UF,+20%/-80%';
 PARENT_PPT = 'CAP_NP';
 PARENT_PPT_PART = 'CAP_NP_SMDCAP-.1UF,+20%/-80%';
 PARENT_CHIPS_PHYS_PART = 'CAP_NP_SMDCAP';
END_LIB_INFO;
END_PRIM;

BEGIN_SIGNAL:
CANON_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):AEN';
LOG_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):AEN';
PHY_SIGNAL = 'AEN';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):BNC2';
LOG_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):BNC2';
PHY_SIGNAL = 'BNC2';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):BNC3';
LOG_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):BNC3';
PHY_SIGNAL = 'BNC3';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):BRD';
LOG_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):BRD';
PHY_SIGNAL = 'BRD';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):BRESET';
LOG_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):BRESET';
PHY_SIGNAL = 'BRESET';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):BWR';
LOG_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):BWR';
PHY_SIGNAL = 'BWR';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):DATA';
LOG_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):DATA';
PHY_SIGNAL = 'DATA';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):DCLK';
LOG_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):DCLK';
PHY_SIGNAL = 'DCLK';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):DDIR';
LOG_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):DDIR';
PHY_SIGNAL = 'DDIR';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):DEN';
LOG_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):DEN';
PHY_SIGNAL = 'DEN';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):DHEN';
LOG_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):DHEN';
PHY_SIGNAL = 'DHEN';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):FPGA';
LOG_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):FPGA';
PHY_SIGNAL = 'FPGA';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):GAIN';
LOG_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):GAIN';
PHY_SIGNAL = 'GAIN';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):HS';
LOG_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):HS';
PHY_SIGNAL = 'HS';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):MCLK';
LOG_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):MCLK';
PHY_SIGNAL = 'MCLK';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):MRD';
LOG_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):MRD';
PHY_SIGNAL = 'MRD';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):MWR';
LOG_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):MWR';
PHY_SIGNAL = 'MWR';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):NCS';
LOG_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):NCS';
PHY_SIGNAL = 'NCS';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):OE';
LOG_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):OE';
PHY_SIGNAL = 'OE';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):OUTA';
LOG_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):OUTA';
PHY_SIGNAL = 'OUTA';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):OUTB';
LOG_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):OUTB';
PHY_SIGNAL = 'OUTB';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):Q0';
LOG_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):Q0';
PHY_SIGNAL = 'Q0';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):Q1';
LOG_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):Q1';
PHY_SIGNAL = 'Q1';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):Q2';
LOG_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):Q2';
PHY_SIGNAL = 'Q2';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):Q3';
LOG_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):Q3';
PHY_SIGNAL = 'Q3';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):Q4';
LOG_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):Q4';
PHY_SIGNAL = 'Q4';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):Q5';
LOG_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):Q5';
PHY_SIGNAL = 'Q5';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):Q6';
LOG_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):Q6';
PHY_SIGNAL = 'Q6';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):Q7';
LOG_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):Q7';
PHY_SIGNAL = 'Q7';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):RCS0';
LOG_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):RCS0';
PHY_SIGNAL = 'RCS0';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):RCS1';
LOG_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):RCS1';
PHY_SIGNAL = 'RCS1';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):RCS2';
LOG_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):RCS2';
PHY_SIGNAL = 'RCS2';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):RCS3';
LOG_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):RCS3';
PHY_SIGNAL = 'RCS3';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):RDY';
LOG_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):RDY';
PHY_SIGNAL = 'RDY';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):RESET';
LOG_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):RESET';
PHY_SIGNAL = 'RESET';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):RWE';
LOG_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):RWE';
PHY_SIGNAL = 'RWE';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):SEL';
LOG_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):SEL';
PHY_SIGNAL = 'SEL';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):VCLKA';
LOG_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):VCLKA';
PHY_SIGNAL = 'VCLKA';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):VCLKC';
LOG_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):VCLKC';
PHY_SIGNAL = 'VCLKC';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):WAIT';
LOG_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):WAIT';
PHY_SIGNAL = 'WAIT';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):WSTAT';
LOG_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):WSTAT';
PHY_SIGNAL = 'WSTAT';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):A(0)';
LOG_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):A(0)';
PHY_SIGNAL = 'A0';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):A(1)';
LOG_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):A(1)';
PHY_SIGNAL = 'A1';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):A(2)';
LOG_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):A(2)';
PHY_SIGNAL = 'A2';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):A(3)';
LOG_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):A(3)';
PHY_SIGNAL = 'A3';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):A(4)';
LOG_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):A(4)';
PHY_SIGNAL = 'A4';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):A(5)';
LOG_SIGNAL = '@PROJECT1_LIB.ROOT(SCH_1):A(5)';
PHY_SIGNAL = 'A5';
END_SIGNAL;

BEGIN_SIGNAL: