pstxprt.dat,2

cadence公司pcb内部培训的资料,并且附带其中的例子程序!比市面上任何一本cadence的书好!

 HAS_FIXED_SIZE='8',
 SIZE='8',
 PRIM_FILE='./classlib/fct16245/chips/chips.prt';

SECTION_NUMBER 12
 '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]16245(CHIPS)'(4):
 C_PATH='@project1_lib.root(sch_1):page1_i7(4)@classlib.fct16245(chips)',
 PATH='I7',
 DRAWING='@PROJECT1_LIB.ROOT(SCH_1):PAGE1',
 XY='(-1000,2500)',
 VER='1',
 ROT='0',
 LOCATION='U4',
 PACK_TYPE='SOIC',
 CDS_LIB='classlib',
 HAS_FIXED_SIZE='8',
 SIZE='8',
 PRIM_FILE='./classlib/fct16245/chips/chips.prt';

SECTION_NUMBER 13
 '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]16245(CHIPS)'(3):
 C_PATH='@project1_lib.root(sch_1):page1_i7(3)@classlib.fct16245(chips)',
 PATH='I7',
 DRAWING='@PROJECT1_LIB.ROOT(SCH_1):PAGE1',
 XY='(-1000,2500)',
 VER='1',
 ROT='0',
 LOCATION='U4',
 PACK_TYPE='SOIC',
 CDS_LIB='classlib',
 HAS_FIXED_SIZE='8',
 SIZE='8',
 PRIM_FILE='./classlib/fct16245/chips/chips.prt';

SECTION_NUMBER 14
 '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]16245(CHIPS)'(2):
 C_PATH='@project1_lib.root(sch_1):page1_i7(2)@classlib.fct16245(chips)',
 PATH='I7',
 DRAWING='@PROJECT1_LIB.ROOT(SCH_1):PAGE1',
 XY='(-1000,2500)',
 VER='1',
 ROT='0',
 LOCATION='U4',
 PACK_TYPE='SOIC',
 CDS_LIB='classlib',
 HAS_FIXED_SIZE='8',
 SIZE='8',
 PRIM_FILE='./classlib/fct16245/chips/chips.prt';

SECTION_NUMBER 15
 '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]16245(CHIPS)'(1):
 C_PATH='@project1_lib.root(sch_1):page1_i7(1)@classlib.fct16245(chips)',
 PATH='I7',
 DRAWING='@PROJECT1_LIB.ROOT(SCH_1):PAGE1',
 XY='(-1000,2500)',
 VER='1',
 ROT='0',
 LOCATION='U4',
 PACK_TYPE='SOIC',
 CDS_LIB='classlib',
 HAS_FIXED_SIZE='8',
 SIZE='8',
 PRIM_FILE='./classlib/fct16245/chips/chips.prt';

SECTION_NUMBER 16
 '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]16245(CHIPS)'(0):
 C_PATH='@project1_lib.root(sch_1):page1_i7(0)@classlib.fct16245(chips)',
 PATH='I7',
 DRAWING='@PROJECT1_LIB.ROOT(SCH_1):PAGE1',
 XY='(-1000,2500)',
 VER='1',
 ROT='0',
 LOCATION='U4',
 PACK_TYPE='SOIC',
 CDS_LIB='classlib',
 HAS_FIXED_SIZE='8',
 SIZE='8',
 PRIM_FILE='./classlib/fct16245/chips/chips.prt';

PART_NAME
 U5 'EPF8282A_PLCC-BASE':;

SECTION_NUMBER 1
 '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]8282A(CHIPS)':
 C_PATH='@project1_lib.root(sch_1):[e-mail]8282a(chips)',
 PATH='I1',
 DRAWING='@PROJECT1_LIB.ROOT(SCH_1):PAGE2',
 XY='(-2800,2800)',
 VER='1',
 ROT='0',
 LOCATION='U5',
 CDS_LIB='classlib',
 PACK_TYPE='PLCC',
 PRIM_FILE='./classlib/epf8282a/chips/chips.prt';

PART_NAME
 U6 'ACT574_SOIC-BASE':
 ROOM='LED';

SECTION_NUMBER 1
 '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]574(CHIPS)':
 C_PATH='@project1_lib.root(sch_1):[e-mail]574(chips)',
 PATH='I2',
 DRAWING='@PROJECT1_LIB.ROOT(SCH_1):PAGE2',
 XY='(600,3300)',
 VER='1',
 ROT='0',
 LOCATION='U6',
 ROOM='LED',
 CDS_LIB='classlib',
 PACK_TYPE='SOIC',
 PRIM_FILE='./classlib/act574/chips/chips.prt';

PART_NAME
 U7 'EPC1064_DIP-BASE':;

SECTION_NUMBER 1
 '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]1064(CHIPS)':
 C_PATH='@project1_lib.root(sch_1):[e-mail]1064(chips)',
 PATH='I18',
 DRAWING='@PROJECT1_LIB.ROOT(SCH_1):PAGE2',
 XY='(-3850,2150)',
 VER='1',
 ROT='0',
 LOCATION='U7',
 PACK_TYPE='DIP',
 CDS_LIB='classlib',
 PRIM_FILE='./classlib/epc1064/chips/chips.prt';

PART_NAME
 U8 'ACT574_SOIC-BASE':
 ROOM='CHAN1';

SECTION_NUMBER 1
 '@PROJECT1_LIB.ROOT(SCH_1):PAGE2_I20@PROJECT1_LIB.DATA(SCH_1):[e-mail]574(CHIPS)':
 C_PATH='@project1_lib.root(sch_1):page2_i20@project1_lib.data(sch_1):page1_i1@c~
lasslib.act574(chips)',
 PATH='I1',
 DRAWING='@PROJECT1_LIB.DATA(SCH_1):PAGE1',
 XY='(-2850,3900)',
 VER='1',
 ROT='0',
 ROOM='CHAN1',
 LOCATION='U8',
 CDS_LIB='classlib',
 PACK_TYPE='SOIC',
 LIBRARY1='ieee',
 USE1='ieee.std_logic_1164.all',
 USE2='work.all',
 PRIM_FILE='./classlib/act574/chips/chips.prt';

PART_NAME
 U9 'ACT574_SOIC-BASE':
 ROOM='CHAN2';

SECTION_NUMBER 1
 '@PROJECT1_LIB.ROOT(SCH_1):PAGE2_I20@PROJECT1_LIB.DATA(SCH_1):[e-mail]574(CHIPS)':
 C_PATH='@project1_lib.root(sch_1):page2_i20@project1_lib.data(sch_1):page1_i2@c~
lasslib.act574(chips)',
 PATH='I2',
 DRAWING='@PROJECT1_LIB.DATA(SCH_1):PAGE1',
 XY='(-2850,2250)',
 VER='1',
 ROT='0',
 ROOM='CHAN2',
 LOCATION='U9',
 CDS_LIB='classlib',
 PACK_TYPE='SOIC',
 LIBRARY1='ieee',
 USE1='ieee.std_logic_1164.all',
 USE2='work.all',
 PRIM_FILE='./classlib/act574/chips/chips.prt';

PART_NAME
 U10 'TC55B4257_SOIC-BASE':
 ROOM='MEM';

SECTION_NUMBER 1
 '@PROJECT1_LIB.ROOT(SCH_1):PAGE2_I19@PROJECT1_LIB.HIGH_SPEED_RAM(SCH_1):[e-mail]55B4257(CHIPS)':
 C_PATH='@project1_lib.root(sch_1):page2_i19@project1_lib.high_speed_ram(sch_1):~
[e-mail]55b4257(chips)',
 PATH='I1',
 DRAWING='@PROJECT1_LIB.HIGH_SPEED_RAM(SCH_1):PAGE1',
 XY='(-1500,3650)',
 VER='1',
 ROT='0',
 ROOM='MEM',
 LOCATION='U10',
 CDS_LIB='classlib',
 PACK_TYPE='SOIC',
 LIBRARY1='ieee',
 USE1='ieee.std_logic_1164.all',
 USE2='work.all',
 PRIM_FILE='./classlib/tc55b4257/chips/chips.prt';

PART_NAME
 U11 'TC55B4257_SOIC-BASE':
 ROOM='MEM';

SECTION_NUMBER 1
 '@PROJECT1_LIB.ROOT(SCH_1):PAGE2_I19@PROJECT1_LIB.HIGH_SPEED_RAM(SCH_1):[e-mail]55B4257(CHIPS)':
 C_PATH='@project1_lib.root(sch_1):page2_i19@project1_lib.high_speed_ram(sch_1):~
[e-mail]55b4257(chips)',
 PATH='I2',
 DRAWING='@PROJECT1_LIB.HIGH_SPEED_RAM(SCH_1):PAGE1',
 XY='(50,3650)',
 VER='1',
 ROT='0',
 LOCATION='U11',
 ROOM='MEM',
 PACK_TYPE='SOIC',
 CDS_LIB='classlib',
 LIBRARY1='ieee',
 USE1='ieee.std_logic_1164.all',
 USE2='work.all',
 PRIM_FILE='./classlib/tc55b4257/chips/chips.prt';

PART_NAME
 U12 'TC55B4257_SOIC-BASE':
 ROOM='MEM';

SECTION_NUMBER 1
 '@PROJECT1_LIB.ROOT(SCH_1):PAGE2_I19@PROJECT1_LIB.HIGH_SPEED_RAM(SCH_1):[e-mail]55B4257(CHIPS)':
 C_PATH='@project1_lib.root(sch_1):page2_i19@project1_lib.high_speed_ram(sch_1):~
[e-mail]55b4257(chips)',
 PATH='I1',
 DRAWING='@PROJECT1_LIB.HIGH_SPEED_RAM(SCH_1):PAGE2',
 XY='(-1100,3650)',
 VER='1',
 ROT='0',
 ROOM='MEM',
 LOCATION='U12',
 PACK_TYPE='SOIC',
 CDS_LIB='classlib',
 LIBRARY1='ieee',
 USE1='ieee.std_logic_1164.all',
 USE2='work.all',
 PRIM_FILE='./classlib/tc55b4257/chips/chips.prt';

PART_NAME
 U13 'TC55B4257_SOIC-BASE':
 ROOM='MEM';

SECTION_NUMBER 1
 '@PROJECT1_LIB.ROOT(SCH_1):PAGE2_I19@PROJECT1_LIB.HIGH_SPEED_RAM(SCH_1):[e-mail]55B4257(CHIPS)':
 C_PATH='@project1_lib.root(sch_1):page2_i19@project1_lib.high_speed_ram(sch_1):~
[e-mail]55b4257(chips)',
 PATH='I27',
 DRAWING='@PROJECT1_LIB.HIGH_SPEED_RAM(SCH_1):PAGE2',
 XY='(650,3650)',
 VER='1',
 ROT='0',
 ROOM='MEM',
 LOCATION='U13',
 PACK_TYPE='SOIC',
 CDS_LIB='classlib',
 LIBRARY1='ieee',
 USE1='ieee.std_logic_1164.all',
 USE2='work.all',
 PRIM_FILE='./classlib/tc55b4257/chips/chips.prt';

PART_NAME
 U14 'TC55B4257_SOIC-BASE':
 ROOM='MEM';

SECTION_NUMBER 1
 '@PROJECT1_LIB.ROOT(SCH_1):PAGE2_I19@PROJECT1_LIB.HIGH_SPEED_RAM(SCH_1):[e-mail]55B4257(CHIPS)':
 C_PATH='@project1_lib.root(sch_1):page2_i19@project1_lib.high_speed_ram(sch_1):~
[e-mail]55b4257(chips)',
 PATH='I8',
 DRAWING='@PROJECT1_LIB.HIGH_SPEED_RAM(SCH_1):PAGE1',
 XY='(-1500,2050)',
 VER='1',
 ROT='0',
 LOCATION='U14',
 ROOM='MEM',
 PACK_TYPE='SOIC',
 CDS_LIB='classlib',
 LIBRARY1='ieee',
 USE1='ieee.std_logic_1164.all',
 USE2='work.all',
 PRIM_FILE='./classlib/tc55b4257/chips/chips.prt';

PART_NAME
 U15 'TC55B4257_SOIC-BASE':
 ROOM='MEM';

SECTION_NUMBER 1
 '@PROJECT1_LIB.ROOT(SCH_1):PAGE2_I19@PROJECT1_LIB.HIGH_SPEED_RAM(SCH_1):[e-mail]55B4257(CHIPS)':
 C_PATH='@project1_lib.root(sch_1):page2_i19@project1_lib.high_speed_ram(sch_1):~
[e-mail]55b4257(chips)',
 PATH='I7',
 DRAWING='@PROJECT1_LIB.HIGH_SPEED_RAM(SCH_1):PAGE1',
 XY='(50,2050)',
 VER='1',
 ROT='0',
 LOCATION='U15',
 ROOM='MEM',
 PACK_TYPE='SOIC',
 CDS_LIB='classlib',
 LIBRARY1='ieee',
 USE1='ieee.std_logic_1164.all',
 USE2='work.all',
 PRIM_FILE='./classlib/tc55b4257/chips/chips.prt';

PART_NAME
 U16 'TC55B4257_SOIC-BASE':
 ROOM='MEM';

SECTION_NUMBER 1
 '@PROJECT1_LIB.ROOT(SCH_1):PAGE2_I19@PROJECT1_LIB.HIGH_SPEED_RAM(SCH_1):[e-mail]55B4257(CHIPS)':
 C_PATH='@project1_lib.root(sch_1):page2_i19@project1_lib.high_speed_ram(sch_1):~
[e-mail]55b4257(chips)',
 PATH='I2',
 DRAWING='@PROJECT1_LIB.HIGH_SPEED_RAM(SCH_1):PAGE2',
 XY='(-1100,2050)',
 VER='1',
 ROT='0',
 ROOM='MEM',
 LOCATION='U16',
 PACK_TYPE='SOIC',
 CDS_LIB='classlib',
 LIBRARY1='ieee',
 USE1='ieee.std_logic_1164.all',
 USE2='work.all',
 PRIM_FILE='./classlib/tc55b4257/chips/chips.prt';

PART_NAME
 U17 'TC55B4257_SOIC-BASE':
 ROOM='MEM';

SECTION_NUMBER 1
 '@PROJECT1_LIB.ROOT(SCH_1):PAGE2_I19@PROJECT1_LIB.HIGH_SPEED_RAM(SCH_1):[e-mail]55B4257(CHIPS)':
 C_PATH='@project1_lib.root(sch_1):page2_i19@project1_lib.high_speed_ram(sch_1):~
[e-mail]55b4257(chips)',
 PATH='I53',
 DRAWING='@PROJECT1_LIB.HIGH_SPEED_RAM(SCH_1):PAGE2',
 XY='(650,2050)',
 VER='1',
 ROT='0',
 ROOM='MEM',
 LOCATION='U17',
 PACK_TYPE='SOIC',
 CDS_LIB='classlib',
 LIBRARY1='ieee',
 USE1='ieee.std_logic_1164.all',
 USE2='work.all',
 PRIM_FILE='./classlib/tc55b4257/chips/chips.prt';

PART_NAME
 U18 'TLC5602_SOIC-BASE':
 ROOM='CHAN1';

SECTION_NUMBER 1
 '@PROJECT1_LIB.ROOT(SCH_1):PAGE2_I20@PROJECT1_LIB.DATA(SCH_1):PAGE1_I56@PROJECT1_LIB.DAAMP(SCH_1):[e-mail]5602(CHIPS)':
 C_PATH='@project1_lib.root(sch_1):page2_i20@project1_lib.data(sch_1):page1_i56@~
project1_lib.daamp(sch_1):[e-mail]5602(chips)',
 PATH='I31',
 DRAWING='@PROJECT1_LIB.DAAMP(SCH_1):PAGE1',
 LOCATION='U18',
 XY='(-1400,2950)',
 VER='1',
 ROT='0',
 CDS_LIB='classlib',
 PACK_TYPE='SOIC',
 ROOM='CHAN1',
 USE2='work.all',
 USE1='ieee.std_logic_1164.all',
 LIBRARY1='ieee',
 PRIM_FILE='./classlib/tlc5602/chips/chips.prt';

PART_NAME
 U19 'DG419_SOIC-BASE':
 ROOM='CHAN1';

SECTION_NUMBER 1
 '@PROJECT1_LIB.ROOT(SCH_1):PAGE2_I20@PROJECT1_LIB.DATA(SCH_1):PAGE1_I56@PROJECT1_LIB.DAAMP(SCH_1):[e-mail]419(CHIPS)':
 C_PATH='@project1_lib.root(sch_1):page2_i20@project1_lib.data(sch_1):page1_i56@~
project1_lib.daamp(sch_1):[e-mail]419(chips)',
 PATH='I6',
 DRAWING='@PROJECT1_LIB.DAAMP(SCH_1):PAGE1',
 XY='(250,3050)',
 VER='1',
 ROT='0',
 CDS_LIB='classlib',
 PACK_TYPE='SOIC',
 ROOM='CHAN1',
 USE2='work.all',
 USE1='ieee.std_logic_1164.all',
 LIBRARY1='ieee',
 PRIM_FILE='./classlib/dg419/chips/chips.prt';

PART_NAME
 U20 'TLE2037_CAN-BASE':
 ROOM='CHAN1';

SECTION_NUMBER 1
 '@PROJECT1_LIB.ROOT(SCH_1):PAGE2_I20@PROJECT1_LIB.DATA(SCH_1):PAGE1_I56@PROJECT1_LIB.DAAMP(SCH_1):[e-mail]2037(CHIPS)':
 C_PATH='@project1_lib.root(sch_1):page2_i20@project1_lib.data(sch_1):page1_i56@~
project1_lib.daamp(sch_1):[e-mail]2037(chips)',
 PATH='I7',
 DRAWING='@PROJECT1_LIB.DAAMP(SCH_1):PAGE1',
 XY='(1950,3100)',
 VER='1',
 ROT='0',
 CDS_LIB='classlib',
 PACK_TYPE='CAN',
 ROOM='CHAN1',
 USE2='work.all',
 USE1='ieee.std_logic_1164.all',
 LIBRARY1='ieee',
 PRIM_FILE='./classlib/tle2037/chips/chips.prt';

PART_NAME
 U21 'TLC5602_SOIC-BASE':
 ROOM='CHAN2';

SECTION_NUMBER 1
 '@PROJECT1_LIB.ROOT(SCH_1):PAGE2_I20@PROJECT1_LIB.DATA(SCH_1):PAGE1_I57@PROJECT1_LIB.DAAMP(SCH_1):[e-mail]5602(CHIPS)':
 C_PATH='@project1_lib.root(sch_1):page2_i20@project1_lib.data(sch_1):page1_i57@~
project1_lib.daamp(sch_1):[e-mail]5602(chips)',
 PATH='I31',
 DRAWING='@PROJECT1_LIB.DAAMP(SCH_1):PAGE1',
 LOCATION='U21',
 XY='(-1400,2950)',
 VER='1',
 ROT='0',
 CDS_LIB='classlib',
 PACK_TYPE='SOIC',
 ROOM='CHAN2',
 USE2='work.all',
 USE1='ieee.std_logic_1164.all',
 LIBRARY1='ieee',
 PRIM_FILE='./classlib/tlc5602/chips/chips.prt';

PART_NAME
 U22 'TLE2037_CAN-BASE':
 ROOM='CHAN2';

SECTION_NUMBER 1
 '@PROJECT1_LIB.ROOT(SCH_1):PAGE2_I20@PROJECT1_LIB.DATA(SCH_1):PAGE1_I57@PROJECT1_LIB.DAAMP(SCH_1):[e-mail]2037(CHIPS)':
 C_PATH='@project1_lib.root(sch_1):page2_i20@project1_lib.data(sch_1):page1_i57@~
project1_lib.daamp(sch_1):[e-mail]2037(chips)',
 PATH='I7',
 DRAWING='@PROJECT1_LIB.DAAMP(SCH_1):PAGE1',
 LOCATION='U22',
 XY='(1950,3100)',
 VER='1',
 ROT='0',
 CDS_LIB='classlib',
 PACK_TYPE='CAN',
 ROOM='CHAN2',
 USE2='work.all',
 USE1='ieee.std_logic_1164.all',
 LIBRARY1='ieee',
 PRIM_FILE='./classlib/tle2037/chips/chips.prt';

PART_NAME
 U23 'DG419_SOIC-BASE':
 ROOM='CHAN2';

SECTION_NUMBER 1
 '@PROJECT1_LIB.ROOT(SCH_1):PAGE2_I20@PROJECT1_LIB.DATA(SCH_1):PAGE1_I57@PROJECT1_LIB.DAAMP(SCH_1):[e-mail]419(CHIPS)':
 C_PATH='@project1_lib.root(sch_1):page2_i20@project1_lib.data(sch_1):page1_i57@~
project1_lib.daamp(sch_1):[e-mail]419(chips)',
 PATH='I6',
 DRAWING='@PROJECT1_LIB.DAAMP(SCH_1):PAGE1',
 LOCATION='U23',
 XY='(250,3050)',
 VER='1',
 ROT='0',
 CDS_LIB='classlib',
 PACK_TYPE='SOIC',
 ROOM='CHAN2',
 USE2='work.all',
 USE1='ieee.std_logic_1164.all',
 LIBRARY1='ieee',
 PRIM_FILE='./classlib/dg419/chips/chips.prt';

END.