pstxprt.dat,2

cadence公司pcb内部培训的资料,并且附带其中的例子程序!比市面上任何一本cadence的书好!

 C_PATH='@project1_lib.root(sch_1):page1_i5(3)@classlib.fct16245(chips)',
 PATH='I5',
 DRAWING='@PROJECT1_LIB.ROOT(SCH_1):PAGE1',
 XY='(-1000,4450)',
 VER='1',
 ROT='0',
 LOCATION='U1',
 PACK_TYPE='SOIC',
 CDS_LIB='classlib',
 HAS_FIXED_SIZE='8',
 SIZE='8',
 PRIM_FILE='./classlib/fct16245/chips/chips.prt';

SECTION_NUMBER 14
 '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]16245(CHIPS)'(2):
 C_PATH='@project1_lib.root(sch_1):page1_i5(2)@classlib.fct16245(chips)',
 PATH='I5',
 DRAWING='@PROJECT1_LIB.ROOT(SCH_1):PAGE1',
 XY='(-1000,4450)',
 VER='1',
 ROT='0',
 LOCATION='U1',
 PACK_TYPE='SOIC',
 CDS_LIB='classlib',
 HAS_FIXED_SIZE='8',
 SIZE='8',
 PRIM_FILE='./classlib/fct16245/chips/chips.prt';

SECTION_NUMBER 15
 '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]16245(CHIPS)'(1):
 C_PATH='@project1_lib.root(sch_1):page1_i5(1)@classlib.fct16245(chips)',
 PATH='I5',
 DRAWING='@PROJECT1_LIB.ROOT(SCH_1):PAGE1',
 XY='(-1000,4450)',
 VER='1',
 ROT='0',
 LOCATION='U1',
 PACK_TYPE='SOIC',
 CDS_LIB='classlib',
 HAS_FIXED_SIZE='8',
 SIZE='8',
 PRIM_FILE='./classlib/fct16245/chips/chips.prt';

SECTION_NUMBER 16
 '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]16245(CHIPS)'(0):
 C_PATH='@project1_lib.root(sch_1):page1_i5(0)@classlib.fct16245(chips)',
 PATH='I5',
 DRAWING='@PROJECT1_LIB.ROOT(SCH_1):PAGE1',
 XY='(-1000,4450)',
 VER='1',
 ROT='0',
 LOCATION='U1',
 PACK_TYPE='SOIC',
 CDS_LIB='classlib',
 HAS_FIXED_SIZE='8',
 SIZE='8',
 PRIM_FILE='./classlib/fct16245/chips/chips.prt';

PART_NAME
 U2 '20L10_DIP-BASE':;

SECTION_NUMBER 1
 '@PROJECT1_LIB.ROOT(SCH_1):PAGE1_I8@CLASSLIB.20L10(CHIPS)':
 C_PATH='@project1_lib.root(sch_1):page1_i8@classlib.\20l10\(chips)',
 PATH='I8',
 DRAWING='@PROJECT1_LIB.ROOT(SCH_1):PAGE1',
 XY='(1500,4400)',
 VER='1',
 ROT='0',
 LOCATION='U2',
 PACK_TYPE='DIP',
 CDS_LIB='classlib',
 PRIM_FILE='./classlib/20l10/chips/chips.prt';

PART_NAME
 U3 'FCT16245_SOIC-BASE':;

SECTION_NUMBER 1
 '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]16245(CHIPS)'(7):
 C_PATH='@project1_lib.root(sch_1):page1_i3(7)@classlib.fct16245(chips)',
 PATH='I3',
 DRAWING='@PROJECT1_LIB.ROOT(SCH_1):PAGE1',
 XY='(-2600,3500)',
 VER='1',
 ROT='0',
 LOCATION='U3',
 PACK_TYPE='SOIC',
 CDS_LIB='classlib',
 HAS_FIXED_SIZE='8',
 SIZE='8',
 PRIM_FILE='./classlib/fct16245/chips/chips.prt';

SECTION_NUMBER 2
 '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]16245(CHIPS)'(6):
 C_PATH='@project1_lib.root(sch_1):page1_i3(6)@classlib.fct16245(chips)',
 PATH='I3',
 DRAWING='@PROJECT1_LIB.ROOT(SCH_1):PAGE1',
 XY='(-2600,3500)',
 VER='1',
 ROT='0',
 LOCATION='U3',
 PACK_TYPE='SOIC',
 CDS_LIB='classlib',
 HAS_FIXED_SIZE='8',
 SIZE='8',
 PRIM_FILE='./classlib/fct16245/chips/chips.prt';

SECTION_NUMBER 3
 '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]16245(CHIPS)'(5):
 C_PATH='@project1_lib.root(sch_1):page1_i3(5)@classlib.fct16245(chips)',
 PATH='I3',
 DRAWING='@PROJECT1_LIB.ROOT(SCH_1):PAGE1',
 XY='(-2600,3500)',
 VER='1',
 ROT='0',
 LOCATION='U3',
 PACK_TYPE='SOIC',
 CDS_LIB='classlib',
 HAS_FIXED_SIZE='8',
 SIZE='8',
 PRIM_FILE='./classlib/fct16245/chips/chips.prt';

SECTION_NUMBER 4
 '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]16245(CHIPS)'(4):
 C_PATH='@project1_lib.root(sch_1):page1_i3(4)@classlib.fct16245(chips)',
 PATH='I3',
 DRAWING='@PROJECT1_LIB.ROOT(SCH_1):PAGE1',
 XY='(-2600,3500)',
 VER='1',
 ROT='0',
 LOCATION='U3',
 PACK_TYPE='SOIC',
 CDS_LIB='classlib',
 HAS_FIXED_SIZE='8',
 SIZE='8',
 PRIM_FILE='./classlib/fct16245/chips/chips.prt';

SECTION_NUMBER 5
 '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]16245(CHIPS)'(3):
 C_PATH='@project1_lib.root(sch_1):page1_i3(3)@classlib.fct16245(chips)',
 PATH='I3',
 DRAWING='@PROJECT1_LIB.ROOT(SCH_1):PAGE1',
 XY='(-2600,3500)',
 VER='1',
 ROT='0',
 LOCATION='U3',
 PACK_TYPE='SOIC',
 CDS_LIB='classlib',
 HAS_FIXED_SIZE='8',
 SIZE='8',
 PRIM_FILE='./classlib/fct16245/chips/chips.prt';

SECTION_NUMBER 6
 '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]16245(CHIPS)'(2):
 C_PATH='@project1_lib.root(sch_1):page1_i3(2)@classlib.fct16245(chips)',
 PATH='I3',
 DRAWING='@PROJECT1_LIB.ROOT(SCH_1):PAGE1',
 XY='(-2600,3500)',
 VER='1',
 ROT='0',
 LOCATION='U3',
 PACK_TYPE='SOIC',
 CDS_LIB='classlib',
 HAS_FIXED_SIZE='8',
 SIZE='8',
 PRIM_FILE='./classlib/fct16245/chips/chips.prt';

SECTION_NUMBER 7
 '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]16245(CHIPS)'(1):
 C_PATH='@project1_lib.root(sch_1):page1_i3(1)@classlib.fct16245(chips)',
 PATH='I3',
 DRAWING='@PROJECT1_LIB.ROOT(SCH_1):PAGE1',
 XY='(-2600,3500)',
 VER='1',
 ROT='0',
 LOCATION='U3',
 PACK_TYPE='SOIC',
 CDS_LIB='classlib',
 HAS_FIXED_SIZE='8',
 SIZE='8',
 PRIM_FILE='./classlib/fct16245/chips/chips.prt';

SECTION_NUMBER 8
 '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]16245(CHIPS)'(0):
 C_PATH='@project1_lib.root(sch_1):page1_i3(0)@classlib.fct16245(chips)',
 PATH='I3',
 DRAWING='@PROJECT1_LIB.ROOT(SCH_1):PAGE1',
 XY='(-2600,3500)',
 VER='1',
 ROT='0',
 LOCATION='U3',
 PACK_TYPE='SOIC',
 CDS_LIB='classlib',
 HAS_FIXED_SIZE='8',
 SIZE='8',
 PRIM_FILE='./classlib/fct16245/chips/chips.prt';

SECTION_NUMBER 9
 '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]16245(CHIPS)'(7):
 C_PATH='@project1_lib.root(sch_1):page1_i6(7)@classlib.fct16245(chips)',
 PATH='I6',
 DRAWING='@PROJECT1_LIB.ROOT(SCH_1):PAGE1',
 XY='(-1000,3500)',
 VER='1',
 ROT='0',
 LOCATION='U3',
 PACK_TYPE='SOIC',
 CDS_LIB='classlib',
 HAS_FIXED_SIZE='8',
 SIZE='8',
 PRIM_FILE='./classlib/fct16245/chips/chips.prt';

SECTION_NUMBER 10
 '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]16245(CHIPS)'(6):
 C_PATH='@project1_lib.root(sch_1):page1_i6(6)@classlib.fct16245(chips)',
 PATH='I6',
 DRAWING='@PROJECT1_LIB.ROOT(SCH_1):PAGE1',
 XY='(-1000,3500)',
 VER='1',
 ROT='0',
 LOCATION='U3',
 PACK_TYPE='SOIC',
 CDS_LIB='classlib',
 HAS_FIXED_SIZE='8',
 SIZE='8',
 PRIM_FILE='./classlib/fct16245/chips/chips.prt';

SECTION_NUMBER 11
 '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]16245(CHIPS)'(5):
 C_PATH='@project1_lib.root(sch_1):page1_i6(5)@classlib.fct16245(chips)',
 PATH='I6',
 DRAWING='@PROJECT1_LIB.ROOT(SCH_1):PAGE1',
 XY='(-1000,3500)',
 VER='1',
 ROT='0',
 LOCATION='U3',
 PACK_TYPE='SOIC',
 CDS_LIB='classlib',
 HAS_FIXED_SIZE='8',
 SIZE='8',
 PRIM_FILE='./classlib/fct16245/chips/chips.prt';

SECTION_NUMBER 12
 '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]16245(CHIPS)'(4):
 C_PATH='@project1_lib.root(sch_1):page1_i6(4)@classlib.fct16245(chips)',
 PATH='I6',
 DRAWING='@PROJECT1_LIB.ROOT(SCH_1):PAGE1',
 XY='(-1000,3500)',
 VER='1',
 ROT='0',
 LOCATION='U3',
 PACK_TYPE='SOIC',
 CDS_LIB='classlib',
 HAS_FIXED_SIZE='8',
 SIZE='8',
 PRIM_FILE='./classlib/fct16245/chips/chips.prt';

SECTION_NUMBER 13
 '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]16245(CHIPS)'(3):
 C_PATH='@project1_lib.root(sch_1):page1_i6(3)@classlib.fct16245(chips)',
 PATH='I6',
 DRAWING='@PROJECT1_LIB.ROOT(SCH_1):PAGE1',
 XY='(-1000,3500)',
 VER='1',
 ROT='0',
 LOCATION='U3',
 PACK_TYPE='SOIC',
 CDS_LIB='classlib',
 HAS_FIXED_SIZE='8',
 SIZE='8',
 PRIM_FILE='./classlib/fct16245/chips/chips.prt';

SECTION_NUMBER 14
 '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]16245(CHIPS)'(2):
 C_PATH='@project1_lib.root(sch_1):page1_i6(2)@classlib.fct16245(chips)',
 PATH='I6',
 DRAWING='@PROJECT1_LIB.ROOT(SCH_1):PAGE1',
 XY='(-1000,3500)',
 VER='1',
 ROT='0',
 LOCATION='U3',
 PACK_TYPE='SOIC',
 CDS_LIB='classlib',
 HAS_FIXED_SIZE='8',
 SIZE='8',
 PRIM_FILE='./classlib/fct16245/chips/chips.prt';

SECTION_NUMBER 15
 '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]16245(CHIPS)'(1):
 C_PATH='@project1_lib.root(sch_1):page1_i6(1)@classlib.fct16245(chips)',
 PATH='I6',
 DRAWING='@PROJECT1_LIB.ROOT(SCH_1):PAGE1',
 XY='(-1000,3500)',
 VER='1',
 ROT='0',
 LOCATION='U3',
 PACK_TYPE='SOIC',
 CDS_LIB='classlib',
 HAS_FIXED_SIZE='8',
 SIZE='8',
 PRIM_FILE='./classlib/fct16245/chips/chips.prt';

SECTION_NUMBER 16
 '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]16245(CHIPS)'(0):
 C_PATH='@project1_lib.root(sch_1):page1_i6(0)@classlib.fct16245(chips)',
 PATH='I6',
 DRAWING='@PROJECT1_LIB.ROOT(SCH_1):PAGE1',
 XY='(-1000,3500)',
 VER='1',
 ROT='0',
 LOCATION='U3',
 PACK_TYPE='SOIC',
 CDS_LIB='classlib',
 HAS_FIXED_SIZE='8',
 SIZE='8',
 PRIM_FILE='./classlib/fct16245/chips/chips.prt';

PART_NAME
 U4 'FCT16245_SOIC-BASE':;

SECTION_NUMBER 1
 '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]16245(CHIPS)'(7):
 C_PATH='@project1_lib.root(sch_1):page1_i4(7)@classlib.fct16245(chips)',
 PATH='I4',
 DRAWING='@PROJECT1_LIB.ROOT(SCH_1):PAGE1',
 XY='(-2600,2500)',
 VER='1',
 ROT='0',
 LOCATION='U4',
 PACK_TYPE='SOIC',
 CDS_LIB='classlib',
 HAS_FIXED_SIZE='8',
 SIZE='8',
 PRIM_FILE='./classlib/fct16245/chips/chips.prt';

SECTION_NUMBER 2
 '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]16245(CHIPS)'(6):
 C_PATH='@project1_lib.root(sch_1):page1_i4(6)@classlib.fct16245(chips)',
 PATH='I4',
 DRAWING='@PROJECT1_LIB.ROOT(SCH_1):PAGE1',
 XY='(-2600,2500)',
 VER='1',
 ROT='0',
 LOCATION='U4',
 PACK_TYPE='SOIC',
 CDS_LIB='classlib',
 HAS_FIXED_SIZE='8',
 SIZE='8',
 PRIM_FILE='./classlib/fct16245/chips/chips.prt';

SECTION_NUMBER 3
 '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]16245(CHIPS)'(5):
 C_PATH='@project1_lib.root(sch_1):page1_i4(5)@classlib.fct16245(chips)',
 PATH='I4',
 DRAWING='@PROJECT1_LIB.ROOT(SCH_1):PAGE1',
 XY='(-2600,2500)',
 VER='1',
 ROT='0',
 LOCATION='U4',
 PACK_TYPE='SOIC',
 CDS_LIB='classlib',
 HAS_FIXED_SIZE='8',
 SIZE='8',
 PRIM_FILE='./classlib/fct16245/chips/chips.prt';

SECTION_NUMBER 4
 '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]16245(CHIPS)'(4):
 C_PATH='@project1_lib.root(sch_1):page1_i4(4)@classlib.fct16245(chips)',
 PATH='I4',
 DRAWING='@PROJECT1_LIB.ROOT(SCH_1):PAGE1',
 XY='(-2600,2500)',
 VER='1',
 ROT='0',
 LOCATION='U4',
 PACK_TYPE='SOIC',
 CDS_LIB='classlib',
 HAS_FIXED_SIZE='8',
 SIZE='8',
 PRIM_FILE='./classlib/fct16245/chips/chips.prt';

SECTION_NUMBER 5
 '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]16245(CHIPS)'(3):
 C_PATH='@project1_lib.root(sch_1):page1_i4(3)@classlib.fct16245(chips)',
 PATH='I4',
 DRAWING='@PROJECT1_LIB.ROOT(SCH_1):PAGE1',
 XY='(-2600,2500)',
 VER='1',
 ROT='0',
 LOCATION='U4',
 PACK_TYPE='SOIC',
 CDS_LIB='classlib',
 HAS_FIXED_SIZE='8',
 SIZE='8',
 PRIM_FILE='./classlib/fct16245/chips/chips.prt';

SECTION_NUMBER 6
 '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]16245(CHIPS)'(2):
 C_PATH='@project1_lib.root(sch_1):page1_i4(2)@classlib.fct16245(chips)',
 PATH='I4',
 DRAWING='@PROJECT1_LIB.ROOT(SCH_1):PAGE1',
 XY='(-2600,2500)',
 VER='1',
 ROT='0',
 LOCATION='U4',
 PACK_TYPE='SOIC',
 CDS_LIB='classlib',
 HAS_FIXED_SIZE='8',
 SIZE='8',
 PRIM_FILE='./classlib/fct16245/chips/chips.prt';

SECTION_NUMBER 7
 '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]16245(CHIPS)'(1):
 C_PATH='@project1_lib.root(sch_1):page1_i4(1)@classlib.fct16245(chips)',
 PATH='I4',
 DRAWING='@PROJECT1_LIB.ROOT(SCH_1):PAGE1',
 XY='(-2600,2500)',
 VER='1',
 ROT='0',
 LOCATION='U4',
 PACK_TYPE='SOIC',
 CDS_LIB='classlib',
 HAS_FIXED_SIZE='8',
 SIZE='8',
 PRIM_FILE='./classlib/fct16245/chips/chips.prt';

SECTION_NUMBER 8
 '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]16245(CHIPS)'(0):
 C_PATH='@project1_lib.root(sch_1):page1_i4(0)@classlib.fct16245(chips)',
 PATH='I4',
 DRAWING='@PROJECT1_LIB.ROOT(SCH_1):PAGE1',
 XY='(-2600,2500)',
 VER='1',
 ROT='0',
 LOCATION='U4',
 PACK_TYPE='SOIC',
 CDS_LIB='classlib',
 HAS_FIXED_SIZE='8',
 SIZE='8',
 PRIM_FILE='./classlib/fct16245/chips/chips.prt';

SECTION_NUMBER 9
 '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]16245(CHIPS)'(7):
 C_PATH='@project1_lib.root(sch_1):page1_i7(7)@classlib.fct16245(chips)',
 PATH='I7',
 DRAWING='@PROJECT1_LIB.ROOT(SCH_1):PAGE1',
 XY='(-1000,2500)',
 VER='1',
 ROT='0',
 LOCATION='U4',
 PACK_TYPE='SOIC',
 CDS_LIB='classlib',
 HAS_FIXED_SIZE='8',
 SIZE='8',
 PRIM_FILE='./classlib/fct16245/chips/chips.prt';

SECTION_NUMBER 10
 '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]16245(CHIPS)'(6):
 C_PATH='@project1_lib.root(sch_1):page1_i7(6)@classlib.fct16245(chips)',
 PATH='I7',
 DRAWING='@PROJECT1_LIB.ROOT(SCH_1):PAGE1',
 XY='(-1000,2500)',
 VER='1',
 ROT='0',
 LOCATION='U4',
 PACK_TYPE='SOIC',
 CDS_LIB='classlib',
 HAS_FIXED_SIZE='8',
 SIZE='8',
 PRIM_FILE='./classlib/fct16245/chips/chips.prt';

SECTION_NUMBER 11
 '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]16245(CHIPS)'(5):
 C_PATH='@project1_lib.root(sch_1):page1_i7(5)@classlib.fct16245(chips)',
 PATH='I7',
 DRAWING='@PROJECT1_LIB.ROOT(SCH_1):PAGE1',
 XY='(-1000,2500)',
 VER='1',
 ROT='0',
 LOCATION='U4',
 PACK_TYPE='SOIC',
 CDS_LIB='classlib',