pstxprt.dat,2

cadence公司pcb内部培训的资料,并且附带其中的例子程序!比市面上任何一本cadence的书好!

 VER='1',
 ROT='0',
 LOCATION='R5',
 TOLERENCE='2%',
 VALUE='2K',
 PACK_TYPE='SMDRES',
 CDS_LIB='classlib',
 PRIM_FILE='./classlib/res/chips/chips.prt';

PART_NAME
 R6 'RES_SMDRES-10K,2%':;

SECTION_NUMBER 1
 '@PROJECT1_LIB.ROOT(SCH_1):PAGE2_I20@PROJECT1_LIB.DATA(SCH_1):[e-mail](CHIPS)':
 C_PATH='@project1_lib.root(sch_1):page2_i20@project1_lib.data(sch_1):page1_i4@c~
lasslib.res(chips)',
 PATH='I4',
 DRAWING='@PROJECT1_LIB.DATA(SCH_1):PAGE1',
 XY='(300,4200)',
 VER='2',
 ROT='4',
 LOCATION='R6',
 VALUE='10K',
 TOLERENCE='2%',
 CDS_LIB='classlib',
 PACK_TYPE='SMDRES',
 LIBRARY1='ieee',
 USE1='ieee.std_logic_1164.all',
 USE2='work.all',
 PRIM_FILE='./classlib/res/chips/chips.prt';

PART_NAME
 R7 'RES_SMDRES-10K,2%':;

SECTION_NUMBER 1
 '@PROJECT1_LIB.ROOT(SCH_1):PAGE2_I20@PROJECT1_LIB.DATA(SCH_1):[e-mail](CHIPS)':
 C_PATH='@project1_lib.root(sch_1):page2_i20@project1_lib.data(sch_1):page1_i6@c~
lasslib.res(chips)',
 PATH='I6',
 DRAWING='@PROJECT1_LIB.DATA(SCH_1):PAGE1',
 XY='(1000,4200)',
 VER='2',
 ROT='4',
 LOCATION='R7',
 VALUE='10K',
 TOLERENCE='2%',
 CDS_LIB='classlib',
 PACK_TYPE='SMDRES',
 LIBRARY1='ieee',
 USE1='ieee.std_logic_1164.all',
 USE2='work.all',
 PRIM_FILE='./classlib/res/chips/chips.prt';

PART_NAME
 R8 'RES_SMDRES-10K,2%':;

SECTION_NUMBER 1
 '@PROJECT1_LIB.ROOT(SCH_1):PAGE2_I20@PROJECT1_LIB.DATA(SCH_1):[e-mail](CHIPS)':
 C_PATH='@project1_lib.root(sch_1):page2_i20@project1_lib.data(sch_1):page1_i8@c~
lasslib.res(chips)',
 PATH='I8',
 DRAWING='@PROJECT1_LIB.DATA(SCH_1):PAGE1',
 XY='(1700,4200)',
 VER='2',
 ROT='4',
 LOCATION='R8',
 VALUE='10K',
 TOLERENCE='2%',
 CDS_LIB='classlib',
 PACK_TYPE='SMDRES',
 LIBRARY1='ieee',
 USE1='ieee.std_logic_1164.all',
 USE2='work.all',
 PRIM_FILE='./classlib/res/chips/chips.prt';

PART_NAME
 R9 'RES_SMDRES-10K,2%':;

SECTION_NUMBER 1
 '@PROJECT1_LIB.ROOT(SCH_1):PAGE2_I20@PROJECT1_LIB.DATA(SCH_1):[e-mail](CHIPS)':
 C_PATH='@project1_lib.root(sch_1):page2_i20@project1_lib.data(sch_1):page1_i10@~
classlib.res(chips)',
 PATH='I10',
 DRAWING='@PROJECT1_LIB.DATA(SCH_1):PAGE1',
 XY='(2400,4200)',
 VER='2',
 ROT='4',
 LOCATION='R9',
 VALUE='10K',
 TOLERENCE='2%',
 CDS_LIB='classlib',
 PACK_TYPE='SMDRES',
 LIBRARY1='ieee',
 USE1='ieee.std_logic_1164.all',
 USE2='work.all',
 PRIM_FILE='./classlib/res/chips/chips.prt';

PART_NAME
 R10 'RES_SMDRES-10K,2%':;

SECTION_NUMBER 1
 '@PROJECT1_LIB.ROOT(SCH_1):PAGE2_I20@PROJECT1_LIB.DATA(SCH_1):[e-mail](CHIPS)':
 C_PATH='@project1_lib.root(sch_1):page2_i20@project1_lib.data(sch_1):page1_i3@c~
lasslib.res(chips)',
 PATH='I3',
 DRAWING='@PROJECT1_LIB.DATA(SCH_1):PAGE1',
 XY='(-50,4200)',
 VER='2',
 ROT='4',
 LOCATION='R10',
 VALUE='10K',
 TOLERENCE='2%',
 CDS_LIB='classlib',
 PACK_TYPE='SMDRES',
 LIBRARY1='ieee',
 USE1='ieee.std_logic_1164.all',
 USE2='work.all',
 PRIM_FILE='./classlib/res/chips/chips.prt';

PART_NAME
 R11 'RES_SMDRES-10K,2%':;

SECTION_NUMBER 1
 '@PROJECT1_LIB.ROOT(SCH_1):PAGE2_I20@PROJECT1_LIB.DATA(SCH_1):[e-mail](CHIPS)':
 C_PATH='@project1_lib.root(sch_1):page2_i20@project1_lib.data(sch_1):page1_i5@c~
lasslib.res(chips)',
 PATH='I5',
 DRAWING='@PROJECT1_LIB.DATA(SCH_1):PAGE1',
 XY='(650,4200)',
 VER='2',
 ROT='4',
 LOCATION='R11',
 VALUE='10K',
 TOLERENCE='2%',
 CDS_LIB='classlib',
 PACK_TYPE='SMDRES',
 LIBRARY1='ieee',
 USE1='ieee.std_logic_1164.all',
 USE2='work.all',
 PRIM_FILE='./classlib/res/chips/chips.prt';

PART_NAME
 R12 'RES_SMDRES-10K,2%':;

SECTION_NUMBER 1
 '@PROJECT1_LIB.ROOT(SCH_1):PAGE2_I20@PROJECT1_LIB.DATA(SCH_1):[e-mail](CHIPS)':
 C_PATH='@project1_lib.root(sch_1):page2_i20@project1_lib.data(sch_1):page1_i7@c~
lasslib.res(chips)',
 PATH='I7',
 DRAWING='@PROJECT1_LIB.DATA(SCH_1):PAGE1',
 XY='(1350,4200)',
 VER='2',
 ROT='4',
 LOCATION='R12',
 VALUE='10K',
 TOLERENCE='2%',
 CDS_LIB='classlib',
 PACK_TYPE='SMDRES',
 LIBRARY1='ieee',
 USE1='ieee.std_logic_1164.all',
 USE2='work.all',
 PRIM_FILE='./classlib/res/chips/chips.prt';

PART_NAME
 R13 'RES_SMDRES-10K,2%':;

SECTION_NUMBER 1
 '@PROJECT1_LIB.ROOT(SCH_1):PAGE2_I20@PROJECT1_LIB.DATA(SCH_1):[e-mail](CHIPS)':
 C_PATH='@project1_lib.root(sch_1):page2_i20@project1_lib.data(sch_1):page1_i9@c~
lasslib.res(chips)',
 PATH='I9',
 DRAWING='@PROJECT1_LIB.DATA(SCH_1):PAGE1',
 XY='(2050,4200)',
 VER='2',
 ROT='4',
 LOCATION='R13',
 VALUE='10K',
 TOLERENCE='2%',
 CDS_LIB='classlib',
 PACK_TYPE='SMDRES',
 LIBRARY1='ieee',
 USE1='ieee.std_logic_1164.all',
 USE2='work.all',
 PRIM_FILE='./classlib/res/chips/chips.prt';

PART_NAME
 R14 'RES_SMDRES-1/4W,2%':
 ROOM='CHAN2';

SECTION_NUMBER 1
 '@PROJECT1_LIB.ROOT(SCH_1):PAGE2_I20@PROJECT1_LIB.DATA(SCH_1):[e-mail](CHIPS)':
 C_PATH='@project1_lib.root(sch_1):page2_i20@project1_lib.data(sch_1):page1_i58@~
classlib.res(chips)',
 PATH='I58',
 DRAWING='@PROJECT1_LIB.DATA(SCH_1):PAGE1',
 XY='(-1750,1250)',
 VER='2',
 ROT='0',
 ROOM='CHAN2',
 TOLERENCE='2%',
 VALUE='1/4W',
 CDS_LIB='classlib',
 PACK_TYPE='SMDRES',
 LIBRARY1='ieee',
 USE1='ieee.std_logic_1164.all',
 USE2='work.all',
 PRIM_FILE='./classlib/res/chips/chips.prt';

PART_NAME
 R15 'RES_SMDRES-100,2%':
 ROOM='CHAN1';

SECTION_NUMBER 1
 '@PROJECT1_LIB.ROOT(SCH_1):PAGE2_I20@PROJECT1_LIB.DATA(SCH_1):PAGE1_I56@PROJECT1_LIB.DAAMP(SCH_1):[e-mail](CHIPS)':
 C_PATH='@project1_lib.root(sch_1):page2_i20@project1_lib.data(sch_1):page1_i56@~
project1_lib.daamp(sch_1):[e-mail](chips)',
 PATH='I9',
 DRAWING='@PROJECT1_LIB.DAAMP(SCH_1):PAGE1',
 LOCATION='R15',
 XY='(300,3650)',
 VER='1',
 ROT='0',
 VALUE='100',
 TOLERENCE='2%',
 CDS_LIB='classlib',
 PACK_TYPE='SMDRES',
 ROOM='CHAN1',
 USE2='work.all',
 USE1='ieee.std_logic_1164.all',
 LIBRARY1='ieee',
 PRIM_FILE='./classlib/res/chips/chips.prt';

PART_NAME
 R16 'RES_SMDRES-100,2%':
 ROOM='CHAN1';

SECTION_NUMBER 1
 '@PROJECT1_LIB.ROOT(SCH_1):PAGE2_I20@PROJECT1_LIB.DATA(SCH_1):PAGE1_I56@PROJECT1_LIB.DAAMP(SCH_1):[e-mail](CHIPS)':
 C_PATH='@project1_lib.root(sch_1):page2_i20@project1_lib.data(sch_1):page1_i56@~
project1_lib.daamp(sch_1):[e-mail](chips)',
 PATH='I10',
 DRAWING='@PROJECT1_LIB.DAAMP(SCH_1):PAGE1',
 LOCATION='R16',
 XY='(300,3950)',
 VER='1',
 ROT='0',
 VALUE='100',
 TOLERENCE='2%',
 CDS_LIB='classlib',
 PACK_TYPE='SMDRES',
 ROOM='CHAN1',
 USE2='work.all',
 USE1='ieee.std_logic_1164.all',
 LIBRARY1='ieee',
 PRIM_FILE='./classlib/res/chips/chips.prt';

PART_NAME
 R17 'RES_SMDRES-100,2%':
 ROOM='CHAN2';

SECTION_NUMBER 1
 '@PROJECT1_LIB.ROOT(SCH_1):PAGE2_I20@PROJECT1_LIB.DATA(SCH_1):PAGE1_I57@PROJECT1_LIB.DAAMP(SCH_1):[e-mail](CHIPS)':
 C_PATH='@project1_lib.root(sch_1):page2_i20@project1_lib.data(sch_1):page1_i57@~
project1_lib.daamp(sch_1):[e-mail](chips)',
 PATH='I9',
 DRAWING='@PROJECT1_LIB.DAAMP(SCH_1):PAGE1',
 LOCATION='R17',
 XY='(300,3650)',
 VER='1',
 ROT='0',
 VALUE='100',
 TOLERENCE='2%',
 CDS_LIB='classlib',
 PACK_TYPE='SMDRES',
 ROOM='CHAN2',
 USE2='work.all',
 USE1='ieee.std_logic_1164.all',
 LIBRARY1='ieee',
 PRIM_FILE='./classlib/res/chips/chips.prt';

PART_NAME
 R18 'RES_SMDRES-100,2%':
 ROOM='CHAN2';

SECTION_NUMBER 1
 '@PROJECT1_LIB.ROOT(SCH_1):PAGE2_I20@PROJECT1_LIB.DATA(SCH_1):PAGE1_I57@PROJECT1_LIB.DAAMP(SCH_1):[e-mail](CHIPS)':
 C_PATH='@project1_lib.root(sch_1):page2_i20@project1_lib.data(sch_1):page1_i57@~
project1_lib.daamp(sch_1):[e-mail](chips)',
 PATH='I10',
 DRAWING='@PROJECT1_LIB.DAAMP(SCH_1):PAGE1',
 LOCATION='R18',
 XY='(300,3950)',
 VER='1',
 ROT='0',
 VALUE='100',
 TOLERENCE='2%',
 CDS_LIB='classlib',
 PACK_TYPE='SMDRES',
 ROOM='CHAN2',
 USE2='work.all',
 USE1='ieee.std_logic_1164.all',
 LIBRARY1='ieee',
 PRIM_FILE='./classlib/res/chips/chips.prt';

PART_NAME
 U1 'FCT16245_SOIC-BASE':;

SECTION_NUMBER 1
 '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]16245(CHIPS)'(7):
 C_PATH='@project1_lib.root(sch_1):page1_i2(7)@classlib.fct16245(chips)',
 PATH='I2',
 DRAWING='@PROJECT1_LIB.ROOT(SCH_1):PAGE1',
 XY='(-2600,4450)',
 VER='1',
 ROT='0',
 PACK_TYPE='SOIC',
 CDS_LIB='classlib',
 HAS_FIXED_SIZE='8',
 SIZE='8',
 PRIM_FILE='./classlib/fct16245/chips/chips.prt';

SECTION_NUMBER 2
 '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]16245(CHIPS)'(6):
 C_PATH='@project1_lib.root(sch_1):page1_i2(6)@classlib.fct16245(chips)',
 PATH='I2',
 DRAWING='@PROJECT1_LIB.ROOT(SCH_1):PAGE1',
 XY='(-2600,4450)',
 VER='1',
 ROT='0',
 PACK_TYPE='SOIC',
 CDS_LIB='classlib',
 HAS_FIXED_SIZE='8',
 SIZE='8',
 PRIM_FILE='./classlib/fct16245/chips/chips.prt';

SECTION_NUMBER 3
 '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]16245(CHIPS)'(5):
 C_PATH='@project1_lib.root(sch_1):page1_i2(5)@classlib.fct16245(chips)',
 PATH='I2',
 DRAWING='@PROJECT1_LIB.ROOT(SCH_1):PAGE1',
 XY='(-2600,4450)',
 VER='1',
 ROT='0',
 PACK_TYPE='SOIC',
 CDS_LIB='classlib',
 HAS_FIXED_SIZE='8',
 SIZE='8',
 PRIM_FILE='./classlib/fct16245/chips/chips.prt';

SECTION_NUMBER 4
 '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]16245(CHIPS)'(4):
 C_PATH='@project1_lib.root(sch_1):page1_i2(4)@classlib.fct16245(chips)',
 PATH='I2',
 DRAWING='@PROJECT1_LIB.ROOT(SCH_1):PAGE1',
 XY='(-2600,4450)',
 VER='1',
 ROT='0',
 PACK_TYPE='SOIC',
 CDS_LIB='classlib',
 HAS_FIXED_SIZE='8',
 SIZE='8',
 PRIM_FILE='./classlib/fct16245/chips/chips.prt';

SECTION_NUMBER 5
 '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]16245(CHIPS)'(3):
 C_PATH='@project1_lib.root(sch_1):page1_i2(3)@classlib.fct16245(chips)',
 PATH='I2',
 DRAWING='@PROJECT1_LIB.ROOT(SCH_1):PAGE1',
 XY='(-2600,4450)',
 VER='1',
 ROT='0',
 PACK_TYPE='SOIC',
 CDS_LIB='classlib',
 HAS_FIXED_SIZE='8',
 SIZE='8',
 PRIM_FILE='./classlib/fct16245/chips/chips.prt';

SECTION_NUMBER 6
 '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]16245(CHIPS)'(2):
 C_PATH='@project1_lib.root(sch_1):page1_i2(2)@classlib.fct16245(chips)',
 PATH='I2',
 DRAWING='@PROJECT1_LIB.ROOT(SCH_1):PAGE1',
 XY='(-2600,4450)',
 VER='1',
 ROT='0',
 PACK_TYPE='SOIC',
 CDS_LIB='classlib',
 HAS_FIXED_SIZE='8',
 SIZE='8',
 PRIM_FILE='./classlib/fct16245/chips/chips.prt';

SECTION_NUMBER 7
 '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]16245(CHIPS)'(1):
 C_PATH='@project1_lib.root(sch_1):page1_i2(1)@classlib.fct16245(chips)',
 PATH='I2',
 DRAWING='@PROJECT1_LIB.ROOT(SCH_1):PAGE1',
 XY='(-2600,4450)',
 VER='1',
 ROT='0',
 PACK_TYPE='SOIC',
 CDS_LIB='classlib',
 HAS_FIXED_SIZE='8',
 SIZE='8',
 PRIM_FILE='./classlib/fct16245/chips/chips.prt';

SECTION_NUMBER 8
 '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]16245(CHIPS)'(0):
 C_PATH='@project1_lib.root(sch_1):page1_i2(0)@classlib.fct16245(chips)',
 PATH='I2',
 DRAWING='@PROJECT1_LIB.ROOT(SCH_1):PAGE1',
 XY='(-2600,4450)',
 VER='1',
 ROT='0',
 PACK_TYPE='SOIC',
 CDS_LIB='classlib',
 HAS_FIXED_SIZE='8',
 SIZE='8',
 PRIM_FILE='./classlib/fct16245/chips/chips.prt';

SECTION_NUMBER 9
 '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]16245(CHIPS)'(7):
 C_PATH='@project1_lib.root(sch_1):page1_i5(7)@classlib.fct16245(chips)',
 PATH='I5',
 DRAWING='@PROJECT1_LIB.ROOT(SCH_1):PAGE1',
 XY='(-1000,4450)',
 VER='1',
 ROT='0',
 LOCATION='U1',
 PACK_TYPE='SOIC',
 CDS_LIB='classlib',
 HAS_FIXED_SIZE='8',
 SIZE='8',
 PRIM_FILE='./classlib/fct16245/chips/chips.prt';

SECTION_NUMBER 10
 '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]16245(CHIPS)'(6):
 C_PATH='@project1_lib.root(sch_1):page1_i5(6)@classlib.fct16245(chips)',
 PATH='I5',
 DRAWING='@PROJECT1_LIB.ROOT(SCH_1):PAGE1',
 XY='(-1000,4450)',
 VER='1',
 ROT='0',
 LOCATION='U1',
 PACK_TYPE='SOIC',
 CDS_LIB='classlib',
 HAS_FIXED_SIZE='8',
 SIZE='8',
 PRIM_FILE='./classlib/fct16245/chips/chips.prt';

SECTION_NUMBER 11
 '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]16245(CHIPS)'(5):
 C_PATH='@project1_lib.root(sch_1):page1_i5(5)@classlib.fct16245(chips)',
 PATH='I5',
 DRAWING='@PROJECT1_LIB.ROOT(SCH_1):PAGE1',
 XY='(-1000,4450)',
 VER='1',
 ROT='0',
 LOCATION='U1',
 PACK_TYPE='SOIC',
 CDS_LIB='classlib',
 HAS_FIXED_SIZE='8',
 SIZE='8',
 PRIM_FILE='./classlib/fct16245/chips/chips.prt';

SECTION_NUMBER 12
 '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]16245(CHIPS)'(4):
 C_PATH='@project1_lib.root(sch_1):page1_i5(4)@classlib.fct16245(chips)',
 PATH='I5',
 DRAWING='@PROJECT1_LIB.ROOT(SCH_1):PAGE1',
 XY='(-1000,4450)',
 VER='1',
 ROT='0',
 LOCATION='U1',
 PACK_TYPE='SOIC',
 CDS_LIB='classlib',
 HAS_FIXED_SIZE='8',
 SIZE='8',
 PRIM_FILE='./classlib/fct16245/chips/chips.prt';

SECTION_NUMBER 13
 '@PROJECT1_LIB.ROOT(SCH_1):[e-mail]16245(CHIPS)'(3):