hdldirect.dat

cadence公司pcb内部培训的资料,并且附带其中的例子程序!比市面上任何一本cadence的书好!

(
 (file_type "hdldirect.dat" "1.0" )
 (design_name "root" )
 (view "sch_1" )
 (modtime "verilog.v" 1020258275 3208 )
 (timescale "1ns/1ns" )
 (cells "CAP" "CAP_NP" "DG419" "INDUCTOR" "RES" "TLC5602" "TLE2037" )
 (global_signals 
  ("glbl" "AGND" "STD_LOGIC" "wire" "" "" )
  ("glbl" "GND" "STD_LOGIC" "supply0" "" "" )
  ("glbl" "V+12" "STD_LOGIC" "wire" "" "" )
  ("glbl" "V12N" "STD_LOGIC" "wire" "" "" )
  ("glbl" "VCC" "STD_LOGIC" "supply1" "" "" ))
 (single_page 
  ("" 
   ("page1_I2" "INDUCTOR" )
   ("page1_I3" "INDUCTOR" )
   ("page1_I4" "CAP" )
   ("page1_I5" "CAP_NP" )
   ("page1_I6" "DG419" )
   ("page1_I7" "TLE2037" )
   ("page1_I8" "CAP" )
   ("page1_I9" "RES" )
   ("page1_I10" "RES" )
   ("page1_I31" "TLC5602" )))
 (multiple_pages ))