hdldirect.dat

cadence公司pcb内部培训的资料,并且附带其中的例子程序!比市面上任何一本cadence的书好!

(
 (file_type "hdldirect.dat" "1.0" )
 (design_name "root" )
 (view "sch_1" )
 (modtime "verilog.v" 1020258274 4016 )
 (timescale "1ns/1ns" )
 (cells "ACT574" "CAP" "DAAMP" "RES" )
 (global_signals 
  ("glbl" "GND" "STD_LOGIC" "supply0" "" "" ))
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   ("page1_I57" "DAAMP" )
   ("page1_I58" "RES" )))
 (multiple_pages ))