verilog.v

来自「cadence公司pcb内部培训的资料,并且附带其中的例子程序!比市面上任何一本」· Verilog 代码 · 共 46 行

// generated by NetAssembler Version 14.00-p003 Oct 18th, 2000 12:00:00 IST
// on Tue Mar 20 15:11:47 2001


`timescale 1ns/1ns

`define scale_fs	* 0.000001000000000
`define scale_ps	* 0.001000000000000
`define scale_ns	* 1.000000000000000
`define scale_us	* 1000.000000000000000
`define scale_ms	* 1000000.000000000000000
`define scale_sec	* 1000000000.000000000000000
`define scale_min	* 60000000000.000000000000000
`define scale_hr	* 3600000000000.000000000000000



module alias_vector (a, a);
 parameter size = 1;
 inout [size-1:0] a;
endmodule

module alias_bit (a, a);
 inout a;
endmodule


module glbl ();
// Verilog global signals module 
  wire agnd;
`ifdef VAN
	wire gnd;
`else
	supply0 gnd;
`endif
  wire gnd_earth;
  wire \v+12 ;
  wire v12n;
`ifdef VAN
	wire vcc;
`else
	supply1 vcc;
`endif
endmodule