vhdl.vhd

cadence公司pcb内部培训的资料,并且附带其中的例子程序!比市面上任何一本cadence的书好!

-- generated by newgenasym Thu Mar 22 14:22:42 2001

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity DG419 is
    port (    
	D:         INOUT  STD_LOGIC;    
	GND:       INOUT  STD_LOGIC;    
	\in\:      INOUT  STD_LOGIC;    
	S1:        INOUT  STD_LOGIC;    
	S2:        INOUT  STD_LOGIC;    
	\v+\:      INOUT  STD_LOGIC;    
	\v-\:      INOUT  STD_LOGIC;    
	VL:        INOUT  STD_LOGIC);
end DG419;