verilog.v

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// generated by newgenasym  Thu Mar 22 14:22:42 2001


module dg419 (d, gnd, in, s1, s2, \v+ , \v- , vl);
    inout d;
    inout gnd;
    inout in;
    inout s1;
    inout s2;
    inout \v+ ;
    inout \v- ;
    inout vl;


    initial
        begin
        end

endmodule