vhdl.vhd

cadence公司pcb内部培训的资料,并且附带其中的例子程序!比市面上任何一本cadence的书好!

-- generated by newgenasym Thu Mar 22 14:27:02 2001

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity EPF8282A is
    port (    
	ADD:       OUT    STD_LOGIC_VECTOR (13 DOWNTO 1);    
	ADD0:      OUT    STD_LOGIC;    
	ADD14:     OUT    STD_LOGIC;    
	ADD15:     OUT    STD_LOGIC;    
	ADD16:     OUT    STD_LOGIC;    
	ADD17:     OUT    STD_LOGIC;    
	ADD18:     OUT    STD_LOGIC;    
	BD:        IN     STD_LOGIC_VECTOR (7 DOWNTO 0);    
	CLKUSR:    OUT    STD_LOGIC;    
	CONF_DONE: IN     STD_LOGIC;    
	DATA0:     IN     STD_LOGIC;    
	DATA1:     IN     STD_LOGIC;    
	DATA2:     IN     STD_LOGIC;    
	DATA3:     IN     STD_LOGIC;    
	DATA4:     IN     STD_LOGIC;    
	DATA5:     IN     STD_LOGIC;    
	DCLK:      IN     STD_LOGIC;    
	GAIN:      OUT    STD_LOGIC;    
	\i/o\:     IN     STD_LOGIC;    
	INPUT:     IN     STD_LOGIC;    
	INPUTA:    IN     STD_LOGIC;    
	INPUTB:    IN     STD_LOGIC;    
	INPUTC:    IN     STD_LOGIC;    
	MSEL0:     IN     STD_LOGIC;    
	MSEL1:     IN     STD_LOGIC;    
	NCONFIG:   IN     STD_LOGIC;    
	NCS:       IN     STD_LOGIC;    
	NRS:       OUT    STD_LOGIC;    
	NSP:       IN     STD_LOGIC;    
	NSTATUS:   IN     STD_LOGIC;    
	NTRST:     IN     STD_LOGIC;    
	NWS:       IN     STD_LOGIC;    
	RD:        OUT    STD_LOGIC_VECTOR (7 DOWNTO 0);    
	RDCLK:     OUT    STD_LOGIC;    
	RDYNBUSY:  OUT    STD_LOGIC;    
	RESET:     IN     STD_LOGIC;    
	TCK:       IN     STD_LOGIC;    
	TDI:       IN     STD_LOGIC;    
	TDO:       IN     STD_LOGIC;    
	VCLKA:     OUT    STD_LOGIC;    
	VCLKB:     OUT    STD_LOGIC;    
	VCLKC:     OUT    STD_LOGIC;    
	VD:        OUT    STD_LOGIC_VECTOR (7 DOWNTO 0));
end EPF8282A;