vhdl.vhd

cadence公司pcb内部培训的资料,并且附带其中的例子程序!比市面上任何一本cadence的书好!

-- generated by newgenasym Thu Mar 22 14:14:53 2001

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity ACT574 is
    port (    
	CLK:       IN     STD_LOGIC;    
	D0:        IN     STD_LOGIC;    
	D1:        IN     STD_LOGIC;    
	D2:        IN     STD_LOGIC;    
	D3:        IN     STD_LOGIC;    
	D4:        IN     STD_LOGIC;    
	D5:        IN     STD_LOGIC;    
	D6:        IN     STD_LOGIC;    
	D7:        IN     STD_LOGIC;    
	OE:        IN     STD_LOGIC;    
	Q0:        INOUT  STD_LOGIC;    
	Q1:        INOUT  STD_LOGIC;    
	Q2:        INOUT  STD_LOGIC;    
	Q3:        INOUT  STD_LOGIC;    
	Q4:        INOUT  STD_LOGIC;    
	Q5:        INOUT  STD_LOGIC;    
	Q6:        INOUT  STD_LOGIC;    
	Q7:        INOUT  STD_LOGIC);
end ACT574;