ad9851.twr

经典的dds发生器ad9851vhdl的并行通信代码

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Release 8.1i Trace I.24
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

E:\tool1\ise8.1\bin\nt\trce.exe -ise ad9851-1.ise -intstyle ise -e 3 -l 3 -s 6
-xml ad9851 ad9851.ncd -o ad9851.twr ad9851.pcf


Design file:              ad9851.ncd
Physical constraint file: ad9851.pcf
Device,speed:             xc2s100,-6 (PRODUCTION 1.27 2005-11-04)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock clk
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
keyin       |    8.056(R)|   -3.225(R)|clk_BUFGP         |   0.000|
rst         |    7.909(R)|   -3.967(R)|clk_BUFGP         |   0.000|
------------+------------+------------+------------------+--------+

Clock clk to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
dds_data<0> |    6.383(R)|clk_BUFGP         |   0.000|
dds_data<1> |    6.414(R)|clk_BUFGP         |   0.000|
dds_data<2> |    6.414(R)|clk_BUFGP         |   0.000|
dds_data<3> |    6.386(R)|clk_BUFGP         |   0.000|
dds_data<4> |    6.382(R)|clk_BUFGP         |   0.000|
dds_data<5> |    6.386(R)|clk_BUFGP         |   0.000|
dds_data<6> |    6.417(R)|clk_BUFGP         |   0.000|
dds_data<7> |    6.417(R)|clk_BUFGP         |   0.000|
dds_fqud    |    6.414(R)|clk_BUFGP         |   0.000|
dds_reset   |    6.414(R)|clk_BUFGP         |   0.000|
dds_wclk    |    8.513(R)|clk_BUFGP         |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |   10.641|         |         |         |
---------------+---------+---------+---------+---------+

Analysis completed Wed Jul 11 09:21:57 2007
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Peak Memory Usage: 89 MB