ad9851.syr

经典的dds发生器ad9851vhdl的并行通信代码

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1988 - Unit <ad9851>: instances <Mcompar__n0009>, <Mcompar__n0031> of unit <LPM_COMPARE_2> and unit <LPM_COMPARE_5> are dual, second instance is removed
WARNING:Xst:1293 - FF/Latch  <control_1_0> has a constant value of 0 in block <ad9851>.
WARNING:Xst:1293 - FF/Latch  <control_1_4> has a constant value of 0 in block <ad9851>.
WARNING:Xst:1293 - FF/Latch  <control_1_5> has a constant value of 0 in block <ad9851>.
WARNING:Xst:1293 - FF/Latch  <control_1_6> has a constant value of 0 in block <ad9851>.
WARNING:Xst:1293 - FF/Latch  <control_1_7> has a constant value of 0 in block <ad9851>.

Optimizing unit <ad9851> ...
WARNING:Xst:1293 - FF/Latch  <control_2_6> has a constant value of 0 in block <ad9851>.
WARNING:Xst:1293 - FF/Latch  <control_2_7> has a constant value of 0 in block <ad9851>.
WARNING:Xst:1293 - FF/Latch  <control_4_0> has a constant value of 0 in block <ad9851>.

Optimizing unit <key> ...
Loading device for application Rf_Device from file 'v100.nph' in environment E:\tool1\ise8.1.

Mapping all equations...
Building and optimizing final netlist ...
INFO:Xst:2261 - The FF/Latch <control_1_1> in Unit <ad9851> is equivalent to the following 2 FFs/Latches, which will be removed : <control_1_2> <control_1_3> 
Found area constraint ratio of 100 (+ 5) on block ad9851, actual ratio is 9.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : ad9851.ngr
Top Level Output File Name         : ad9851
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 26

Cell Usage :
# BELS                             : 309
#      GND                         : 1
#      INV                         : 10
#      LUT1_L                      : 42
#      LUT2                        : 18
#      LUT2_D                      : 1
#      LUT2_L                      : 5
#      LUT3                        : 22
#      LUT3_L                      : 2
#      LUT4                        : 44
#      LUT4_D                      : 4
#      LUT4_L                      : 59
#      MUXCY                       : 57
#      MUXF5                       : 5
#      VCC                         : 1
#      XORCY                       : 38
# FlipFlops/Latches                : 82
#      FD                          : 25
#      FDC                         : 27
#      FDCE                        : 3
#      FDE                         : 27
# Clock Buffers                    : 2
#      BUFG                        : 1
#      BUFGP                       : 1
# IO Buffers                       : 25
#      IBUF                        : 2
#      OBUF                        : 23
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s100pq208-6 

 Number of Slices:                     110  out of   1200     9%  
 Number of Slice Flip Flops:            82  out of   2400     3%  
 Number of 4 input LUTs:               197  out of   2400     8%  
 Number of bonded IOBs:                 26  out of    144    18%  
 Number of GCLKs:                        2  out of      4    50%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 57    |
u1/keyout1                         | BUFG                   | 25    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 12.709ns (Maximum Frequency: 78.684MHz)
   Minimum input arrival time before clock: 9.757ns
   Maximum output required time after clock: 8.903ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 12.709ns (frequency: 78.684MHz)
  Total number of paths / destination ports: 11255 / 87
-------------------------------------------------------------------------
Delay:               12.709ns (Levels of Logic = 28)
  Source:            u1/qq_0 (FF)
  Destination:       u1/qq_1 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: u1/qq_0 to u1/qq_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              4   1.085   1.440  u1/qq_0 (u1/qq_0)
     INV:I->O              1   0.549   0.000  u1/key__n0005<0>lut_INV_0 (u1/N4)
     MUXCY:S->O            1   0.659   0.000  u1/key__n0005<0>cy (u1/key__n0005<0>_cyo)
     MUXCY:CI->O           1   0.042   0.000  u1/key__n0005<1>cy (u1/key__n0005<1>_cyo)
     MUXCY:CI->O           1   0.042   0.000  u1/key__n0005<2>cy (u1/key__n0005<2>_cyo)
     MUXCY:CI->O           1   0.042   0.000  u1/key__n0005<3>cy (u1/key__n0005<3>_cyo)
     MUXCY:CI->O           1   0.042   0.000  u1/key__n0005<4>cy (u1/key__n0005<4>_cyo)
     MUXCY:CI->O           1   0.042   0.000  u1/key__n0005<5>cy (u1/key__n0005<5>_cyo)
     MUXCY:CI->O           1   0.042   0.000  u1/key__n0005<6>cy (u1/key__n0005<6>_cyo)
     MUXCY:CI->O           1   0.042   0.000  u1/key__n0005<7>cy (u1/key__n0005<7>_cyo)
     MUXCY:CI->O           1   0.042   0.000  u1/key__n0005<8>cy (u1/key__n0005<8>_cyo)
     MUXCY:CI->O           1   0.042   0.000  u1/key__n0005<9>cy (u1/key__n0005<9>_cyo)
     MUXCY:CI->O           1   0.042   0.000  u1/key__n0005<10>cy (u1/key__n0005<10>_cyo)
     MUXCY:CI->O           1   0.042   0.000  u1/key__n0005<11>cy (u1/key__n0005<11>_cyo)
     MUXCY:CI->O           1   0.042   0.000  u1/key__n0005<12>cy (u1/key__n0005<12>_cyo)
     MUXCY:CI->O           1   0.042   0.000  u1/key__n0005<13>cy (u1/key__n0005<13>_cyo)
     MUXCY:CI->O           1   0.042   0.000  u1/key__n0005<14>cy (u1/key__n0005<14>_cyo)
     MUXCY:CI->O           1   0.042   0.000  u1/key__n0005<15>cy (u1/key__n0005<15>_cyo)
     MUXCY:CI->O           1   0.042   0.000  u1/key__n0005<16>cy (u1/key__n0005<16>_cyo)
     MUXCY:CI->O           1   0.042   0.000  u1/key__n0005<17>cy (u1/key__n0005<17>_cyo)
     MUXCY:CI->O           1   0.042   0.000  u1/key__n0005<18>cy (u1/key__n0005<18>_cyo)
     MUXCY:CI->O           1   0.042   0.000  u1/key__n0005<19>cy (u1/key__n0005<19>_cyo)
     MUXCY:CI->O           1   0.042   0.000  u1/key__n0005<20>cy (u1/key__n0005<20>_cyo)
     MUXCY:CI->O           1   0.042   0.000  u1/key__n0005<21>cy (u1/key__n0005<21>_cyo)
     XORCY:CI->O           9   0.420   1.908  u1/key__n0005<22>_xor (u1/_n0005<22>)
     LUT3:I2->O            1   0.549   1.035  u1/Ker1111 (u1/Ker11_map153)
     LUT4_L:I3->LO         1   0.549   0.000  u1/Ker1164_G (N361)
     MUXF5:I1->O          11   0.305   2.070  u1/Ker1164 (u1/Ker11_map166)
     LUT4_L:I3->LO         1   0.549   0.000  u1/_n0003<7>1 (u1/_n0003<7>)
     FDC:D                     0.709          u1/qq_7
    ----------------------------------------
    Total                     12.709ns (6.256ns logic, 6.453ns route)
                                       (49.2% logic, 50.8% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'u1/keyout1'
  Clock period: 6.528ns (frequency: 153.186MHz)
  Total number of paths / destination ports: 93 / 25
-------------------------------------------------------------------------
Delay:               6.528ns (Levels of Logic = 1)
  Source:            kk_0 (FF)
  Destination:       kk_0 (FF)
  Source Clock:      u1/keyout1 rising
  Destination Clock: u1/keyout1 rising

  Data Path: kk_0 to kk_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q              26   1.085   3.150  kk_0 (kk_0)
     INV:I->O              1   0.549   1.035  _n0026<0>1_INV_0 (_n0026<0>)
     FD:D                      0.709          kk_0
    ----------------------------------------
    Total                      6.528ns (2.343ns logic, 4.185ns route)
                                       (35.9% logic, 64.1% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
  Total number of paths / destination ports: 62 / 52
-------------------------------------------------------------------------
Offset:              9.757ns (Levels of Logic = 5)
  Source:            keyin (PAD)
  Destination:       u1/keyout (FF)
  Destination Clock: clk rising

  Data Path: keyin to u1/keyout
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            31   0.776   3.375  keyin_IBUF (keyin_IBUF)
     LUT3_L:I1->LO         1   0.549   0.100  u1/Ker67 (u1/Ker6_map110)
     LUT4:I1->O            1   0.549   1.035  u1/Ker619 (u1/Ker6_map114)
     LUT4:I0->O            5   0.549   1.566  u1/Ker646 (u1/N6)
     LUT4_L:I3->LO         1   0.549   0.000  u1/_n0003<13>1 (u1/_n0003<13>)
     FDC:D                     0.709          u1/qq_13
    ----------------------------------------
    Total                      9.757ns (3.681ns logic, 6.076ns route)
                                       (37.7% logic, 62.3% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 11 / 11
-------------------------------------------------------------------------
Offset:              6.959ns (Levels of Logic = 1)
  Source:            dds_wclk (FF)
  Destination:       dds_wclk (PAD)
  Source Clock:      clk rising

  Data Path: dds_wclk to dds_wclk
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             2   1.085   1.206  dds_wclk (dds_wclk_OBUF)
     OBUF:I->O                 4.668          dds_wclk_OBUF (dds_wclk)
    ----------------------------------------
    Total                      6.959ns (5.753ns logic, 1.206ns route)
                                       (82.7% logic, 17.3% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'u1/keyout1'
  Total number of paths / destination ports: 3 / 3
-------------------------------------------------------------------------
Offset:              8.903ns (Levels of Logic = 1)
  Source:            kk_0 (FF)
  Destination:       seg<0> (PAD)
  Source Clock:      u1/keyout1 rising

  Data Path: kk_0 to seg<0>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q              26   1.085   3.150  kk_0 (kk_0)
     OBUF:I->O                 4.668          seg_0_OBUF (seg<0>)
    ----------------------------------------
    Total                      8.903ns (5.753ns logic, 3.150ns route)
                                       (64.6% logic, 35.4% route)

=========================================================================
CPU : 16.52 / 17.80 s | Elapsed : 16.00 / 17.00 s
 
--> 

Total memory usage is 106296 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :   11 (   0 filtered)
Number of infos    :    2 (   0 filtered)