elec_lock.cmp.rpt

本程序是用VHDL语言实现电子密码锁功能,整个系统分为三大模块,一为控制模块,二为键盘显示模块,三为处理模块

Compilation report for elec_lock
Mon Aug 06 10:38:56 2007
Version 5.1 Build 176 10/26/2005 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Flow Summary
  3. Flow Settings
  4. Flow Elapsed Time
  5. Flow Log
  6. Analysis & Synthesis Summary
  7. Analysis & Synthesis Settings
  8. Analysis & Synthesis Source Files Read
  9. Analysis & Synthesis Resource Usage Summary
 10. Analysis & Synthesis Resource Utilization by Entity
 11. General Register Statistics
 12. Parameter Settings for Inferred Entity Instance: lpm_counter:\counter:Q[0]_rtl_0
 13. Analysis & Synthesis Equations
 14. Analysis & Synthesis Messages
 15. Fitter Summary
 16. Fitter Settings
 17. Fitter Device Options
 18. Fitter Equations
 19. Input Pins
 20. Output Pins
 21. All Package Pins
 22. Control Signals
 23. Global & Other Fast Signals
 24. Carry Chains
 25. Cascade Chains
 26. Non-Global High Fan-Out Signals
 27. Peripheral Signals
 28. LAB
 29. Local Routing Interconnect
 30. LAB External Interconnect
 31. Row Interconnect
 32. LAB Column Interconnect
 33. LAB Column Interconnect
 34. Fitter Resource Usage Summary
 35. Fitter Resource Utilization by Entity
 36. Delay Chain Summary
 37. Pin-Out File
 38. Fitter Messages
 39. Assembler Summary
 40. Assembler Settings
 41. Assembler Generated Files
 42. Assembler Device Options: F:/备赛资料/VHDL模块/elec_lock/elec_lock.sof
 43. Assembler Device Options: F:/备赛资料/VHDL模块/elec_lock/elec_lock.pof
 44. Assembler Messages
 45. Timing Analyzer Summary
 46. Timing Analyzer Settings
 47. Clock Settings Summary
 48. Clock Setup: 'CLK_4M'
 49. Clock Hold: 'CLK_4M'
 50. tco
 51. Minimum tco
 52. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------+
; Flow Summary                                                       ;
+-------------------------+------------------------------------------+
; Flow Status             ; Successful - Mon Aug 06 10:38:55 2007    ;
; Quartus II Version      ; 5.1 Build 176 10/26/2005 SJ Full Version ;
; Revision Name           ; elec_lock                                ;
; Top-level Entity Name   ; elec_lock                                ;
; Family                  ; FLEX10K                                  ;
; Device                  ; EPF10K10LC84-4                           ;
; Timing Models           ; Final                                    ;
; Met timing requirements ; No                                       ;
; Total logic elements    ; 123 / 576 ( 21 % )                       ;
; Total pins              ; 41 / 59 ( 69 % )                         ;
; Total memory bits       ; 0 / 6,144 ( 0 % )                        ;
+-------------------------+------------------------------------------+


+-----------------------------------------+
; Flow Settings                           ;
+-------------------+---------------------+
; Option            ; Setting             ;
+-------------------+---------------------+
; Start date & time ; 08/06/2007 10:38:32 ;
; Main task         ; Compilation         ;
; Revision Name     ; elec_lock           ;
+-------------------+---------------------+


+-------------------------------------+
; Flow Elapsed Time                   ;
+----------------------+--------------+
; Module Name          ; Elapsed Time ;
+----------------------+--------------+
; Analysis & Synthesis ; 00:00:05     ;
; Fitter               ; 00:00:09     ;
; Assembler            ; 00:00:02     ;
; Timing Analyzer      ; 00:00:02     ;
; Total                ; 00:00:18     ;
+----------------------+--------------+


------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off elec_lock -c elec_lock
quartus_fit --read_settings_files=off --write_settings_files=off elec_lock -c elec_lock
quartus_asm --read_settings_files=off --write_settings_files=off elec_lock -c elec_lock
quartus_tan --read_settings_files=off --write_settings_files=off elec_lock -c elec_lock



+------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                           ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Mon Aug 06 10:38:37 2007    ;
; Quartus II Version          ; 5.1 Build 176 10/26/2005 SJ Full Version ;
; Revision Name               ; elec_lock                                ;
; Top-level Entity Name       ; elec_lock                                ;
; Family                      ; FLEX10K                                  ;
; Total logic elements        ; 123                                      ;
; Total pins                  ; 41                                       ;
; Total memory bits           ; 0                                        ;
+-----------------------------+------------------------------------------+


+---------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                               ;
+------------------------------------------------------------+----------------+---------------+
; Option                                                     ; Setting        ; Default Value ;
+------------------------------------------------------------+----------------+---------------+
; Device                                                     ; EPF10K10LC84-4 ;               ;
; Top-level entity name                                      ; elec_lock      ; elec_lock     ;
; Family name                                                ; FLEX10K        ; Stratix       ;
; Use smart compilation                                      ; Off            ; Off           ;
; Create Debugging Nodes for IP Cores                        ; Off            ; Off           ;
; Preserve fewer node names                                  ; On             ; On            ;
; Disable OpenCore Plus hardware evaluation                  ; Off            ; Off           ;
; Verilog Version                                            ; Verilog_2001   ; Verilog_2001  ;
; VHDL Version                                               ; VHDL93         ; VHDL93        ;
; State Machine Processing                                   ; Auto           ; Auto          ;
; Extract Verilog State Machines                             ; On             ; On            ;
; Extract VHDL State Machines                                ; On             ; On            ;
; Add Pass-Through Logic to Inferred RAMs                    ; On             ; On            ;
; NOT Gate Push-Back                                         ; On             ; On            ;
; Power-Up Don't Care                                        ; On             ; On            ;
; Remove Redundant Logic Cells                               ; Off            ; Off           ;
; Remove Duplicate Registers                                 ; On             ; On            ;