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Verilog实现的DDS正弦信号发生器和测频测相模块

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Adjust:AdjustU0
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Adjust:AdjustU0|Strobe:ScanClockDivider
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Adapter:AdapterU0
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Adapter:AdapterU0|FreFindTable:FreFindTableU0
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Adapter:AdapterU0|FreFindTable:FreFindTableU0|altsyncram:altsyncram_component
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Adapter:AdapterU0|FreFindTable:FreFindTableU0|altsyncram:altsyncram_component|altsyncram_fp21:auto_generated
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Adapter:AdapterU0|PhaseFindTable:PhaseFindTableU0
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Adapter:AdapterU0|PhaseFindTable:PhaseFindTableU0|altsyncram:altsyncram_component
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Adapter:AdapterU0|PhaseFindTable:PhaseFindTableU0|altsyncram:altsyncram_component|altsyncram_4331:auto_generated
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DDS:DDSU0
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DDS:DDSU0|Accumulater:AccumulaterU0
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DDS:DDSU0|SinFindTable:SinFindTableU0
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DDS:DDSU0|SinFindTable:SinFindTableU0|altsyncram:altsyncram_component
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DDS:DDSU0|SinFindTable:SinFindTableU0|altsyncram:altsyncram_component|altsyncram_v531:auto_generated
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DDS:DDSU0|SinFindTable:SinFindTableU1
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DDS:DDSU0|SinFindTable:SinFindTableU1|altsyncram:altsyncram_component
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DDS:DDSU0|SinFindTable:SinFindTableU1|altsyncram:altsyncram_component|altsyncram_v531:auto_generated
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Measure:MeasureU0
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Measure:MeasureU0|Strobe:SystemClockDivider
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Read:ReadU0
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