prev_cmp_workonebeta.tan.qmsg

Verilog实现的DDS正弦信号发生器和测频测相模块

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "3 " "Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "Measure:MeasureU0\|And " "Info: Detected gated clock \"Measure:MeasureU0\|And\" as buffer" {  } { { "Measure.v" "" { Text "F:/电赛/Quartus/WorkOneBetaC/Measure.v" 52 -1 0 } } { "e:/program files/quartus ii/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/program files/quartus ii/quartus/bin/Assignment Editor.qase" 1 { { 0 "Measure:MeasureU0\|And" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "Measure:MeasureU0\|rCountFinishFlag " "Info: Detected ripple clock \"Measure:MeasureU0\|rCountFinishFlag\" as buffer" {  } { { "Measure.v" "" { Text "F:/电赛/Quartus/WorkOneBetaC/Measure.v" 165 -1 0 } } { "e:/program files/quartus ii/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/program files/quartus ii/quartus/bin/Assignment Editor.qase" 1 { { 0 "Measure:MeasureU0\|rCountFinishFlag" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "Adjust:AdjustU0\|Strobe:ScanClockDivider\|rVirtualClock " "Info: Detected ripple clock \"Adjust:AdjustU0\|Strobe:ScanClockDivider\|rVirtualClock\" as buffer" {  } { { "Strobe.v" "" { Text "F:/电赛/Quartus/WorkOneBetaC/Strobe.v" 17 -1 0 } } { "e:/program files/quartus ii/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/program files/quartus ii/quartus/bin/Assignment Editor.qase" 1 { { 0 "Adjust:AdjustU0\|Strobe:ScanClockDivider\|rVirtualClock" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "SysClock register Adjust:AdjustU0\|rSetFrequency\[4\] memory Adapter:AdapterU0\|FreFindTable:FreFindTableU0\|altsyncram:altsyncram_component\|altsyncram_fp21:auto_generated\|ram_block1a13~porta_address_reg4 115.19 MHz 8.681 ns Internal " "Info: Clock \"SysClock\" has Internal fmax of 115.19 MHz between source register \"Adjust:AdjustU0\|rSetFrequency\[4\]\" and destination memory \"Adapter:AdapterU0\|FreFindTable:FreFindTableU0\|altsyncram:altsyncram_component\|altsyncram_fp21:auto_generated\|ram_block1a13~porta_address_reg4\" (period= 8.681 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.744 ns + Longest register memory " "Info: + Longest register to memory delay is 3.744 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Adjust:AdjustU0\|rSetFrequency\[4\] 1 REG LC_X12_Y4_N5 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y4_N5; Fanout = 5; REG Node = 'Adjust:AdjustU0\|rSetFrequency\[4\]'" {  } { { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "" { Adjust:AdjustU0|rSetFrequency[4] } "NODE_NAME" } } { "Adjust.v" "" { Text "F:/电赛/Quartus/WorkOneBetaC/Adjust.v" 107 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.338 ns) + CELL(0.114 ns) 1.452 ns Adjust:AdjustU0\|rSetFrequency\[4\]~_wirecell 2 COMB LC_X12_Y5_N5 6 " "Info: 2: + IC(1.338 ns) + CELL(0.114 ns) = 1.452 ns; Loc. = LC_X12_Y5_N5; Fanout = 6; COMB Node = 'Adjust:AdjustU0\|rSetFrequency\[4\]~_wirecell'" {  } { { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "1.452 ns" { Adjust:AdjustU0|rSetFrequency[4] Adjust:AdjustU0|rSetFrequency[4]~_wirecell } "NODE_NAME" } } { "Adjust.v" "" { Text "F:/电赛/Quartus/WorkOneBetaC/Adjust.v" 107 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.909 ns) + CELL(0.383 ns) 3.744 ns Adapter:AdapterU0\|FreFindTable:FreFindTableU0\|altsyncram:altsyncram_component\|altsyncram_fp21:auto_generated\|ram_block1a13~porta_address_reg4 3 MEM M4K_X13_Y1 4 " "Info: 3: + IC(1.909 ns) + CELL(0.383 ns) = 3.744 ns; Loc. = M4K_X13_Y1; Fanout = 4; MEM Node = 'Adapter:AdapterU0\|FreFindTable:FreFindTableU0\|altsyncram:altsyncram_component\|altsyncram_fp21:auto_generated\|ram_block1a13~porta_address_reg4'" {  } { { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "2.292 ns" { Adjust:AdjustU0|rSetFrequency[4]~_wirecell Adapter:AdapterU0|FreFindTable:FreFindTableU0|altsyncram:altsyncram_component|altsyncram_fp21:auto_generated|ram_block1a13~porta_address_reg4 } "NODE_NAME" } } { "db/altsyncram_fp21.tdf" "" { Text "F:/电赛/Quartus/WorkOneBetaC/db/altsyncram_fp21.tdf" 303 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.497 ns ( 13.27 % ) " "Info: Total cell delay = 0.497 ns ( 13.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.247 ns ( 86.73 % ) " "Info: Total interconnect delay = 3.247 ns ( 86.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "3.744 ns" { Adjust:AdjustU0|rSetFrequency[4] Adjust:AdjustU0|rSetFrequency[4]~_wirecell Adapter:AdapterU0|FreFindTable:FreFindTableU0|altsyncram:altsyncram_component|altsyncram_fp21:auto_generated|ram_block1a13~porta_address_reg4 } "NODE_NAME" } } { "e:/program files/quartus ii/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/quartus ii/quartus/bin/Technology_Viewer.qrui" "3.744 ns" { Adjust:AdjustU0|rSetFrequency[4] Adjust:AdjustU0|rSetFrequency[4]~_wirecell Adapter:AdapterU0|FreFindTable:FreFindTableU0|altsyncram:altsyncram_component|altsyncram_fp21:auto_generated|ram_block1a13~porta_address_reg4 } { 0.000ns 1.338ns 1.909ns } { 0.000ns 0.114ns 0.383ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-4.620 ns - Smallest " "Info: - Smallest clock skew is -4.620 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SysClock destination 2.754 ns + Shortest memory " "Info: + Shortest clock path from clock \"SysClock\" to destination memory is 2.754 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns SysClock 1 CLK PIN_17 319 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 319; CLK Node = 'SysClock'" {  } { { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "" { SysClock } "NODE_NAME" } } { "WorkOne.v" "" { Text "F:/电赛/Quartus/WorkOneBetaC/WorkOne.v" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.563 ns) + CELL(0.722 ns) 2.754 ns Adapter:AdapterU0\|FreFindTable:FreFindTableU0\|altsyncram:altsyncram_component\|altsyncram_fp21:auto_generated\|ram_block1a13~porta_address_reg4 2 MEM M4K_X13_Y1 4 " "Info: 2: + IC(0.563 ns) + CELL(0.722 ns) = 2.754 ns; Loc. = M4K_X13_Y1; Fanout = 4; MEM Node = 'Adapter:AdapterU0\|FreFindTable:FreFindTableU0\|altsyncram:altsyncram_component\|altsyncram_fp21:auto_generated\|ram_block1a13~porta_address_reg4'" {  } { { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "1.285 ns" { SysClock Adapter:AdapterU0|FreFindTable:FreFindTableU0|altsyncram:altsyncram_component|altsyncram_fp21:auto_generated|ram_block1a13~porta_address_reg4 } "NODE_NAME" } } { "db/altsyncram_fp21.tdf" "" { Text "F:/电赛/Quartus/WorkOneBetaC/db/altsyncram_fp21.tdf" 303 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.191 ns ( 79.56 % ) " "Info: Total cell delay = 2.191 ns ( 79.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.563 ns ( 20.44 % ) " "Info: Total interconnect delay = 0.563 ns ( 20.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "2.754 ns" { SysClock Adapter:AdapterU0|FreFindTable:FreFindTableU0|altsyncram:altsyncram_component|altsyncram_fp21:auto_generated|ram_block1a13~porta_address_reg4 } "NODE_NAME" } } { "e:/program files/quartus ii/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/quartus ii/quartus/bin/Technology_Viewer.qrui" "2.754 ns" { SysClock SysClock~out0 Adapter:AdapterU0|FreFindTable:FreFindTableU0|altsyncram:altsyncram_component|altsyncram_fp21:auto_generated|ram_block1a13~porta_address_reg4 } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.722ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SysClock source 7.374 ns - Longest register " "Info: - Longest clock path from clock \"SysClock\" to source register is 7.374 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns SysClock 1 CLK PIN_17 319 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 319; CLK Node = 'SysClock'" {  } { { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "" { SysClock } "NODE_NAME" } } { "WorkOne.v" "" { Text "F:/电赛/Quartus/WorkOneBetaC/WorkOne.v" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.606 ns) + CELL(0.935 ns) 3.010 ns Adjust:AdjustU0\|Strobe:ScanClockDivider\|rVirtualClock 2 REG LC_X26_Y6_N2 21 " "Info: 2: + IC(0.606 ns) + CELL(0.935 ns) = 3.010 ns; Loc. = LC_X26_Y6_N2; Fanout = 21; REG Node = 'Adjust:AdjustU0\|Strobe:ScanClockDivider\|rVirtualClock'" {  } { { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "1.541 ns" { SysClock Adjust:AdjustU0|Strobe:ScanClockDivider|rVirtualClock } "NODE_NAME" } } { "Strobe.v" "" { Text "F:/电赛/Quartus/WorkOneBetaC/Strobe.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.653 ns) + CELL(0.711 ns) 7.374 ns Adjust:AdjustU0\|rSetFrequency\[4\] 3 REG LC_X12_Y4_N5 5 " "Info: 3: + IC(3.653 ns) + CELL(0.711 ns) = 7.374 ns; Loc. = LC_X12_Y4_N5; Fanout = 5; REG Node = 'Adjust:AdjustU0\|rSetFrequency\[4\]'" {  } { { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "4.364 ns" { Adjust:AdjustU0|Strobe:ScanClockDivider|rVirtualClock Adjust:AdjustU0|rSetFrequency[4] } "NODE_NAME" } } { "Adjust.v" "" { Text "F:/电赛/Quartus/WorkOneBetaC/Adjust.v" 107 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 42.24 % ) " "Info: Total cell delay = 3.115 ns ( 42.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.259 ns ( 57.76 % ) " "Info: Total interconnect delay = 4.259 ns ( 57.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "7.374 ns" { SysClock Adjust:AdjustU0|Strobe:ScanClockDivider|rVirtualClock Adjust:AdjustU0|rSetFrequency[4] } "NODE_NAME" } } { "e:/program files/quartus ii/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/quartus ii/quartus/bin/Technology_Viewer.qrui" "7.374 ns" { SysClock SysClock~out0 Adjust:AdjustU0|Strobe:ScanClockDivider|rVirtualClock Adjust:AdjustU0|rSetFrequency[4] } { 0.000ns 0.000ns 0.606ns 3.653ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "2.754 ns" { SysClock Adapter:AdapterU0|FreFindTable:FreFindTableU0|altsyncram:altsyncram_component|altsyncram_fp21:auto_generated|ram_block1a13~porta_address_reg4 } "NODE_NAME" } } { "e:/program files/quartus ii/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/quartus ii/quartus/bin/Technology_Viewer.qrui" "2.754 ns" { SysClock SysClock~out0 Adapter:AdapterU0|FreFindTable:FreFindTableU0|altsyncram:altsyncram_component|altsyncram_fp21:auto_generated|ram_block1a13~porta_address_reg4 } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.722ns } "" } } { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "7.374 ns" { SysClock Adjust:AdjustU0|Strobe:ScanClockDivider|rVirtualClock Adjust:AdjustU0|rSetFrequency[4] } "NODE_NAME" } } { "e:/program files/quartus ii/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/quartus ii/quartus/bin/Technology_Viewer.qrui" "7.374 ns" { SysClock SysClock~out0 Adjust:AdjustU0|Strobe:ScanClockDivider|rVirtualClock Adjust:AdjustU0|rSetFrequency[4] } { 0.000ns 0.000ns 0.606ns 3.653ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "Adjust.v" "" { Text "F:/电赛/Quartus/WorkOneBetaC/Adjust.v" 107 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.093 ns + " "Info: + Micro setup delay of destination is 0.093 ns" {  } { { "db/altsyncram_fp21.tdf" "" { Text "F:/电赛/Quartus/WorkOneBetaC/db/altsyncram_fp21.tdf" 303 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "3.744 ns" { Adjust:AdjustU0|rSetFrequency[4] Adjust:AdjustU0|rSetFrequency[4]~_wirecell Adapter:AdapterU0|FreFindTable:FreFindTableU0|altsyncram:altsyncram_component|altsyncram_fp21:auto_generated|ram_block1a13~porta_address_reg4 } "NODE_NAME" } } { "e:/program files/quartus ii/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/quartus ii/quartus/bin/Technology_Viewer.qrui" "3.744 ns" { Adjust:AdjustU0|rSetFrequency[4] Adjust:AdjustU0|rSetFrequency[4]~_wirecell Adapter:AdapterU0|FreFindTable:FreFindTableU0|altsyncram:altsyncram_component|altsyncram_fp21:auto_generated|ram_block1a13~porta_address_reg4 } { 0.000ns 1.338ns 1.909ns } { 0.000ns 0.114ns 0.383ns } "" } } { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "2.754 ns" { SysClock Adapter:AdapterU0|FreFindTable:FreFindTableU0|altsyncram:altsyncram_component|altsyncram_fp21:auto_generated|ram_block1a13~porta_address_reg4 } "NODE_NAME" } } { "e:/program files/quartus ii/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/quartus ii/quartus/bin/Technology_Viewer.qrui" "2.754 ns" { SysClock SysClock~out0 Adapter:AdapterU0|FreFindTable:FreFindTableU0|altsyncram:altsyncram_component|altsyncram_fp21:auto_generated|ram_block1a13~porta_address_reg4 } { 0.000ns 0.000ns 0.563ns } { 0.000ns 1.469ns 0.722ns } "" } } { "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/quartus ii/quartus/bin/TimingClosureFloorplan.fld" "" "7.374 ns" { SysClock Adjust:AdjustU0|Strobe:ScanClockDivider|rVirtualClock Adjust:AdjustU0|rSetFrequency[4] } "NODE_NAME" } } { "e:/program files/quartus ii/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/quartus ii/quartus/bin/Technology_Viewer.qrui" "7.374 ns" { SysClock SysClock~out0 Adjust:AdjustU0|Strobe:ScanClockDivider|rVirtualClock Adjust:AdjustU0|rSetFrequency[4] } { 0.000ns 0.000ns 0.606ns 3.653ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}