workonebeta.cbx.xml

Verilog实现的DDS正弦信号发生器和测频测相模块

<?xml version="1.0" ?>
<LOG_ROOT>
	<PROJECT NAME="WorkOneBeta">
		<CBX_INST_ENTRY INSTANCE_NAME="|TopLayer|Adapter:AdapterU0|FreFindTable:FreFindTableU0|altsyncram:altsyncram_component" CBX_FILE_NAME="altsyncram_fp21.tdf"/>
		<CBX_INST_ENTRY INSTANCE_NAME="|TopLayer|Adapter:AdapterU0|PhaseFindTable:PhaseFindTableU0|altsyncram:altsyncram_component" CBX_FILE_NAME="altsyncram_4331.tdf"/>
		<CBX_INST_ENTRY INSTANCE_NAME="|TopLayer|DDS:DDSU0|SinFindTable:SinFindTableU0|altsyncram:altsyncram_component" CBX_FILE_NAME="altsyncram_v531.tdf"/>
		<CBX_INST_ENTRY INSTANCE_NAME="|TopLayer|DDS:DDSU0|SinFindTable:SinFindTableU1|altsyncram:altsyncram_component" CBX_FILE_NAME="altsyncram_v531.tdf"/>
	</PROJECT>
</LOG_ROOT>