measure.v.bak

Verilog实现的DDS正弦信号发生器和测频测相模块

module Measure(
Reset,
Start,
Clock,
InputWaveOne,
InputWaveTwo,
FreClockCounter,
FreWaveCounter,
PhaseClockCounter, 
PhaseWaveCounter,
CountFinishFlag,
/* 20070818 */
IndicatorLight,
IndicatorLightB
);
input Reset;
input Start;
input Clock;
input InputWaveOne;
input InputWaveTwo;
output [31:0] FreClockCounter;
output [31:0] FreWaveCounter;
output [31:0] PhaseClockCounter;
output [31:0] PhaseWaveCounter;
output CountFinishFlag;
output IndicatorLight;
output IndicatorLightB;

reg rIndicatorLight;
assign IndicatorLight = rIndicatorLight;

reg rIndicatorLightB;
assign IndicatorLightB = rIndicatorLightB;

reg [31:0] rFreClockCounter;
reg [31:0] rFreWaveCounter;
reg [31:0] rPhaseClockCounter;
reg [31:0] rPhaseWaveCounter;

assign FreClockCounter = rFreClockCounter;
assign FreWaveCounter = rFreWaveCounter;
assign PhaseClockCounter = rPhaseClockCounter;
assign PhaseWaveCounter = rPhaseWaveCounter;

wire StrobeWave;
Strobe SystemClockDivider(.SystemClock(Clock), .(10000000), .VirtualClock(StrobeWave));

/* 将两路信号异或之后再和系统时钟求与 */
wire XorWave;
xor Xor(XorWave, InputWaveOne, InputWaveTwo); 
wire NarrowPulse; 
and And(NarrowPulse, Clock, XorWave);

/* 脉冲计数 */
reg rCountFinishFlag;
assign CountFinishFlag = rCountFinishFlag;

reg rStartExsitFlag;

//always @ (posedge Clear or posedge Clock)
//begin
//  if (1 == Clear)
//  begin
//    rFreClockCounter <= 32'd0;
//    rPhaseClockCounter <= 32'd0;
//  end
//  else
//  begin
//    if (0 == rCountFinishFlag)
//    begin
//      if (1 == StrobeWave)
//      begin
//	    rFreClockCounter <= rFreClockCounter + 32'd1;
//	    //rFreClockCounter <= 32'hf0f0f0f0;
//	    rPhaseClockCounter <= rPhaseClockCounter + 32'd1;
//	    //rPhaseClockCounter <= 32'hffff0000;
//	  end
////	  else
////	  begin
////	    if (32'd1000000 < rFreClockCounter)
////      rCountFinishFlag <= 1; 
////	  rIndicatorLight <= 0;
////	  rStartExsitFlag <= 0;
////	  end
//	end
//  end
//end
//
//always @ (posedge Reset or posedge Start or posedge Clear or posedge InputWaveOne)
//begin
//  if (1 == Reset)
//  begin
//    rCountFinishFlag <= 0;
//    rIndicatorLight <= 1;
//    rStartExsitFlag <= 0;
//  end
//  else if (1 == Start)
//  begin
//    rCountFinishFlag <= 0;
//    rIndicatorLight <= 1;
//    rStartExsitFlag <= 1;
//  end
//  else if(1 == Clear)
//  begin
//    rFreWaveCounter <= 32'd0;
//  end
//  else 
//  begin
//    if (0 == rCountFinishFlag)
//    begin
//      if (1 == StrobeWave)
//      begin
//	    rFreWaveCounter <= rFreWaveCounter + 32'd1;
//        //rFreWaveCounter <= 32'h00000000;
//	  end
//	  else
//	  begin
//	    //if (1 == rStartExsitFlag)
//	    begin 
//          rCountFinishFlag <= 1; 
//	      rIndicatorLight <= 0;
//	      rStartExsitFlag <= 0;
//	    end
//	  end
//	end
//  end
//end
always @ (posedge Reset or posedge Start or posedge Clock)
begin
  if (1 == Reset)
  begin
    rCountFinishFlag <= 0;
    rIndicatorLight <= 1;
    rStartExsitFlag <= 0;
  end
  else if (1 == Start)
  begin
    rCountFinishFlag <= 0;
    rIndicatorLight <= 1;
    rStartExsitFlag <= 1;

    rFreClockCounter <= 32'd0;
    rPhaseClockCounter <= 32'd0;
  end
  else
  begin
    if (0 == rCountFinishFlag)
    begin
      if (1 == StrobeWave)
      begin
	    rFreClockCounter <= rFreClockCounter + 32'd1;
	    //rFreClockCounter <= 32'hf0f0f0f0;
	    rPhaseClockCounter <= rPhaseClockCounter + 32'd1;
	  end
	  else
	  begin
	    if ((1 == rStartExsitFlag) && (0 != rFreClockCounter))
	    begin 
          rCountFinishFlag <= 1; 
	      rIndicatorLight <= 0;
	      rStartExsitFlag <= 0;
	    end
	  end
	end
  end
end

always @ (posedge Start or posedge InputWaveOne)
begin
  if (1 == Start)
  begin
    rFreWaveCounter <= 32'd0;
  end
  else
  begin
    if (0 == rCountFinishFlag)
    begin
      if (1 == StrobeWave)
      begin
	    rIndicatorLightB <= ~rIndicatorLightB;
	    rFreWaveCounter <= rFreWaveCounter + 32'd1;
	  end
//	  else
//	  begin
//	    if (32'd1000000 < rFreClockCounter)
//      rCountFinishFlag <= 1; 
//	  rIndicatorLight <= 0;
//	  rStartExsitFlag <= 0;
//	  end
	end
  end
end

always @ (posedge Start or posedge NarrowPulse)
begin
  if  (1 == Start)
  begin
    rPhaseWaveCounter <= 32'd0;
  end
  else 
  begin
    if (0 == rCountFinishFlag)
    begin
      if (1 == StrobeWave)
      begin
	    rPhaseWaveCounter <= rPhaseWaveCounter + 32'd1;
        //rPhaseWaveCounter <= 32'h00000000;
	  end
	end
  end
end

//always @ (posedge Clear or posedge Clock)
//begin
//  if (1 == Clear)
//  begin
//    rFreClockCounter <= 32'd0;
//    rPhaseClockCounter <= 32'd0;
//  end
//  else 
//  begin
//  if (0 == rCountFinishFlag)
//  begin
//    if (1 == StrobeWave)
//    begin
//	  rFreClockCounter <= rFreClockCounter + 32'd1;
//	  //rFreClockCounter <= 32'hf0f0f0f0;
//	  rPhaseClockCounter <= rPhaseClockCounter + 32'd1;
//	  //rPhaseClockCounter <= 32'hffff0000;
//	end
//  end
//  end
//end
//
//always @ (posedge Clear or posedge InputWaveOne)
//begin
//  if (1 == Clear)
//  begin
//    rFreWaveCounter <= 32'd0;
//  end
//  else
//  begin
//  if (0 == rCountFinishFlag)
//    begin
//      if (1 == StrobeWave)
//      begin
// 	    rFreWaveCounter <= rFreWaveCounter + 32'd1;
//        //rFreWaveCounter <= 32'h00000000;
//	  end
//    end
//  end
//end
//
//always @ (posedge Clear or posedge NarrowPulse)
//begin
//  if (1 == Clear)
//  begin
//      rPhaseWaveCounter <= 32'd0;
//  end
//  else
//  begin
//    if (0 == rCountFinishFlag)
//    begin
//      if (1 == StrobeWave)
//      begin
//	    rPhaseWaveCounter <= rPhaseWaveCounter + 32'd1;
//	    //rPhaseWaveCounter <= 32'hffffffff;
//	  end
//    end
//  end
//end

endmodule