workonebeta.tan.summary

Verilog实现的DDS正弦信号发生器和测频测相模块

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 5.772 ns
From           : Increase
To             : Adjust:AdjustU0|rSetPhase[0]
From Clock     : --
To Clock       : SysClock
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 15.607 ns
From           : PhasaeLeadJudge
To             : LeadFlag
From Clock     : WaveInTwo
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 4.995 ns
From           : SysClock
To             : ClockOut
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 6.689 ns
From           : WaveInOne
To             : PhasaeLeadJudge
From Clock     : --
To Clock       : WaveInTwo
Failed Paths   : 0

Type           : Clock Setup: 'SysClock'
Slack          : N/A
Required Time  : None
Actual Time    : 115.77 MHz ( period = 8.638 ns )
From           : Adjust:AdjustU0|rSetFrequency[4]
To             : Adapter:AdapterU0|FreFindTable:FreFindTableU0|altsyncram:altsyncram_component|altsyncram_fp21:auto_generated|ram_block1a9~porta_address_reg4
From Clock     : SysClock
To Clock       : SysClock
Failed Paths   : 0

Type           : Clock Setup: 'ReadClock'
Slack          : N/A
Required Time  : None
Actual Time    : 127.62 MHz ( period = 7.836 ns )
From           : Read:ReadU0|Counter[4]
To             : Read:ReadU0|tempbit
From Clock     : ReadClock
To Clock       : ReadClock
Failed Paths   : 0

Type           : Clock Setup: 'WaveInOne'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 275.03 MHz ( period = 3.636 ns )
From           : Measure:MeasureU0|rPhaseWaveCounter[0]
To             : Measure:MeasureU0|rPhaseWaveCounter[31]
From Clock     : WaveInOne
To Clock       : WaveInOne
Failed Paths   : 0

Type           : Clock Setup: 'WaveInTwo'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 275.03 MHz ( period = 3.636 ns )
From           : Measure:MeasureU0|rPhaseWaveCounter[0]
To             : Measure:MeasureU0|rPhaseWaveCounter[31]
From Clock     : WaveInTwo
To Clock       : WaveInTwo
Failed Paths   : 0

Type           : Clock Hold: 'SysClock'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : Measure:MeasureU0|rFreClockCounter[30]
To             : Read:ReadU0|SourceData[94]
From Clock     : SysClock
To Clock       : SysClock
Failed Paths   : 64

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 64

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