prev_cmp_workonebeta.qmsg

Verilog实现的DDS正弦信号发生器和测频测相模块

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Create Symbol File Quartus II " "Info: Running Quartus II Create Symbol File" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Aug 21 22:05:03 2007 " "Info: Processing started: Tue Aug 21 22:05:03 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off WorkOneBeta -c WorkOneBeta --generate_symbol=F:\\电赛\\Quartus\\WorkOneBetaC\\Adjust.v " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off WorkOneBeta -c WorkOneBeta --generate_symbol=F:\\电赛\\Quartus\\WorkOneBetaC\\Adjust.v" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Create Symbol File 0 s 0 s Quartus II " "Info: Quartus II Create Symbol File was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "131 " "Info: Allocated 131 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Aug 21 22:05:04 2007 " "Info: Processing ended: Tue Aug 21 22:05:04 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}