workonebeta.sim.rpt

Verilog实现的DDS正弦信号发生器和测频测相模块

; Add pins automatically to simulation output waveforms                                      ; On         ; On            ;
; Check outputs                                                                              ; Off        ; Off           ;
; Report simulation coverage                                                                 ; On         ; On            ;
; Display complete 1/0 value coverage report                                                 ; On         ; On            ;
; Display missing 1-value coverage report                                                    ; On         ; On            ;
; Display missing 0-value coverage report                                                    ; On         ; On            ;
; Detect setup and hold time violations                                                      ; Off        ; Off           ;
; Detect glitches                                                                            ; Off        ; Off           ;
; Disable timing delays in Timing Simulation                                                 ; Off        ; Off           ;
; Generate Signal Activity File                                                              ; Off        ; Off           ;
; Generate VCD File for PowerPlay Power Analyzer                                             ; Off        ; Off           ;
; Group bus channels in simulation results                                                   ; Off        ; Off           ;
; Preserve fewer signal transitions to reduce memory requirements                            ; On         ; On            ;
; Trigger vector comparison with the specified mode                                          ; INPUT_EDGE ; INPUT_EDGE    ;
; Disable setup and hold time violations detection in input registers of bi-directional pins ; Off        ; Off           ;
; Overwrite Waveform Inputs With Simulation Outputs                                          ; On         ;               ;
; Perform Glitch Filtering in Timing Simulation                                              ; Auto       ; Auto          ;
+--------------------------------------------------------------------------------------------+------------+---------------+


+----------------------+
; Simulation Waveforms ;
+----------------------+
Waveform report data cannot be output to ASCII.
Please use Quartus II to view the waveform report data.


+---------------------------------------------------------------------------------------------------------------------------+
; |TopLayer|DDS:DDSU0|SinFindTable:SinFindTableU0|altsyncram:altsyncram_component|altsyncram_v531:auto_generated|ALTSYNCRAM ;
+---------------------------------------------------------------------------------------------------------------------------+
Memory report data cannot be output to ASCII.
Please use Quartus II to view the memory report data.


+---------------------------------------------------------------------------------------------------------------------------+
; |TopLayer|DDS:DDSU0|SinFindTable:SinFindTableU1|altsyncram:altsyncram_component|altsyncram_v531:auto_generated|ALTSYNCRAM ;
+---------------------------------------------------------------------------------------------------------------------------+
Memory report data cannot be output to ASCII.
Please use Quartus II to view the memory report data.


+-----------------------------------------------------------------------------------------------------------------------------------+
; |TopLayer|Adapter:AdapterU0|FreFindTable:FreFindTableU0|altsyncram:altsyncram_component|altsyncram_fp21:auto_generated|ALTSYNCRAM ;
+-----------------------------------------------------------------------------------------------------------------------------------+
Memory report data cannot be output to ASCII.
Please use Quartus II to view the memory report data.


+---------------------------------------------------------------------------------------------------------------------------------------+
; |TopLayer|Adapter:AdapterU0|PhaseFindTable:PhaseFindTableU0|altsyncram:altsyncram_component|altsyncram_4331:auto_generated|ALTSYNCRAM ;
+---------------------------------------------------------------------------------------------------------------------------------------+
Memory report data cannot be output to ASCII.
Please use Quartus II to view the memory report data.


+--------------------------------------------------------------------+
; Coverage Summary                                                   ;
+-----------------------------------------------------+--------------+
; Type                                                ; Value        ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage                      ;       0.00 % ;
; Total nodes checked                                 ; 251          ;
; Total output ports checked                          ; 393          ;
; Total output ports with complete 1/0-value coverage ; 0            ;
; Total output ports with no 1/0-value coverage       ; 393          ;
; Total output ports with no 1-value coverage         ; 393          ;
; Total output ports with no 0-value coverage         ; 393          ;
+-----------------------------------------------------+--------------+