strobe.v.bak

Verilog实现的DDS正弦信号发生器和测频测相模块

module Strobe(SystemClock, DivideValue, VirtualClock);
input SystemClock;
input [27:0] DivideValue;
output VirtualClock;

//wire VirtualClock;
reg rVirtualClock;
assign VirtualClock = rVirtualClock;

reg [27:0] Count; 

//parameter OscFrequency = 10000000;
//parameter OutputFrequency = 2000000;
  
//parameter Threshold = 10000000; 

always @ (posedge SystemClock)
begin
  if(Count < DivideValue - 1)
    begin
	  Count <= Count + 28'd1;
	end
  else
	begin
	  Count = 28'd0;
	  rVirtualClock = ~rVirtualClock;
	end
end
endmodule