adjust.v.bak

Verilog实现的DDS正弦信号发生器和测频测相模块

module Adjust
(
Reset,
ScanClcok,
Select,
Increase,
Decrease,
Double,
Halve,
SetFrequency,
SetPhase,
IndicatorLight
);
input Reset;
input ScanClcok;
input Select;
input Increase;
input Decrease;
input Double;
input Halve;
output [9:0] SetFrequency;
output [8:0] SetPhase;
output IndicatorLight;

//wire Reset;
//wire Select;
//wire Increase;
//wire Decrease;
//wire Double;
//wire Halve;
//wire [14:0] SetFrequency;
//wire [8:0] SetPhase;

reg [9:0] rSetFrequency;
reg [8:0] rSetPhase;
assign SetFrequency = rSetFrequency;
assign SetPhase = rSetPhase;

reg rIndicatorLight;
assign IndicatorLight = rIndicatorLight;

wire SlowClock;
Strobe ScanClockDivider(.SystemClock(ScanClcok), .DivideValue(25), .VirtualClock(SlowClock));


always @ (posedge Reset or posedge SlowClock)
begin
  if (1 == Reset)  /* 复位 */
  begin
    rSetFrequency <= 10'd50;  //DefaultFrequency = 1k
    rSetPhase <= 9'd90;      //DefaultPhase = 90
  end 
  else
  begin
    if (Increase)
    begin
      if (1 == Select)
      begin
        rIndicatorLight <= 0;
        rSetFrequency <= SetFrequency + 10'd1;
      end
      else
      begin
        rIndicatorLight <= 1;
        rSetPhase <= rSetPhase + 9'd1;
      end
    end
    else if (Decrease)
    begin
      if (1 == Select)
      begin
        rIndicatorLight <= 0;
        rSetFrequency <= rSetFrequency - 10'd1;
      end
      else
      begin
        rIndicatorLight <= 1;
        rSetPhase <= rSetPhase - 9'd1;
      end
    end
    else if (Double)
    begin
      if (1 == Select)
      begin
        rIndicatorLight <= 0;
        rSetFrequency <= rSetFrequency<<1;
      end
      else
      begin
        rIndicatorLight <= 1;
        rSetPhase <= rSetPhase<<1;
     end
    end
    else if (Halve)
    begin
      if (1 == Select)
      begin
        rIndicatorLight <= 0;
        rSetFrequency <= rSetFrequency>>1;
      end
      else
      begin
        rIndicatorLight <= 1;
        rSetPhase <= rSetPhase>>1;
      end
    end
  end
end

endmodule