workonebeta.fit.summary

Verilog实现的DDS正弦信号发生器和测频测相模块

Fitter Status : Successful - Tue Aug 21 22:08:33 2007
Quartus II Version : 7.1 Build 156 04/30/2007 SJ Full Version
Revision Name : WorkOneBeta
Top-level Entity Name : TopLayer
Family : Cyclone
Device : EP1C3T144C8
Timing Models : Final
Total logic elements : 426 / 2,910 ( 15 % )
Total pins : 50 / 104 ( 48 % )
Total virtual pins : 0
Total memory bits : 51,718 / 59,904 ( 86 % )
Total PLLs : 0 / 1 ( 0 % )